How to Suppress assertions error from procedure block in VHDL

SystemVerilog
1

Hi All,
I am using COM1905 module, it’s in VHDL and has Block RAMs as well. It has LABELS and Block RAMS as well in the code. Below shows short detail of the Assertion message. How to disable these assertions or change severity of these?

ASSERT/ERROR (time 138346 PS) from procedure ast_mnc_tb_top.mnc_channel.mnc_ip.modem_ip_top_module.COM1905_top:CONV_DECODER_001:FEC_DECODER_004:VA_000:VA_TBU2_001:BRAM_DP_00x(0):Inst_BRAM_DP:RAMB16_S32_S32gen:RAMB16_S36_S36_inst:R1:TDP:RAMB36E1_TDP_inst:prcd_chk_for_col_msg (architecture uni
sim.RB36_INTERNAL_VHDL:RB36_INTERNAL_VHDL_V)
Memory Collision Error on RAMB36E1

Regards,
Sudhanshu

2

You should contact your IP provider or the vendor of your tool for specific instructions on how to disable error messages.