I am currently moving from Modelsim to Questa. One use we used Modelsim for was the code coverage capability, however we always seemed to have to edit/parse the outputs in order to generate a truly accurate code coverage statistic.
In the past the main issue with code coverage was its ability to differentiate between VHDL with generate statements, where the code coverage never actually knew if the generate statements where used.
Does anyone know if Questa has this same issue?