Synchronization issue with clock in D Flip-Flop

UVM
1

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I am facing an issue. Could you help me figure out why dout is not synchronized with clk when using both posedge and negedge in the always block even when I give posedge separately. But its working when I use combinational statement like
assign dout = (rst) ? 0 : din;
What might be the issue?

2

Very hard to debug your issue without seeing all the code as text (not a picture of it) or even a link to the code.

One think I do see is your stimulus is in a race condition with the clock. Use the negative edge to apply stimulus.

3

Okay Sir. In that case let me share you my code link.
Link ā€“ EDA Playground

4

Sir, Even after applying negative egde. It fails!. What to do?

5

Iā€™m not sure if you are right. I made a few modifications. And plese see here:

6

Actually, The mistake was in design. It was not rectified.
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Thank you for the suggestions.