Need to get a constraint with in the 2KB boundary

SystemVerilog
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Hi Team,

I need to constraint a for start_address & end_address and this range should be in b/w 1KB and boundary of the address should not exceed 2KB.

EX: if start_address is 10, then the end_address should be <= 10+1KB . the start_address and end_address should be <=1KB. and total address range should be <=2048.(2KB).

Currently i have written the constraint as below. But it is not working …
constraint c1 {((end_address -start_address)< (1024+start_address)) <=2048;}

Can any one pls help me with this constraint.
Thanks in advance.

2

I used your error as a common mistake in Asking better questions on the Verification Academy Forums with EDAPlayground - Verification Horizons (your question was asked correctly :slight_smile: )

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