1. Agenda & Details Container

    1. Agenda:

      Agenda

      10:00 AM – 10:25 AM

      • Registration and Check-in
        Coffee and networking with your peers

      10:25 AM– 10:30 AM

      • Welcome and Introductions
        Harsh Patel | Sr. AE Manager, Functional Verification

      10:30 AM – 11:15 AM

      • Understanding and Navigating the New Challenges in Design-for-Test
        Lee Harrison | Director of Product Marketing – Tessent

      11:15 AM - Noon

      • Accelerating Verification Closure with Siemens DFT Tailored Verification Solutions
        Jake Wiltgen | Director, IC Verification Solutions

      Noon – 12:30 PM

      • Lunch and Networking

      12:30 PM - 1:15 PM

      • Embracing a New Era in DFT: Addressing High Defect Coverage, Silent Data Errors, and Emerging Challenges
        Lee Harrison | Director of Product Marketing – Tessent

      1:15 PM - 2:00 PM

      • Increasing Fault Coverage with Siemens Functional Fault Grading Solutions
        Ann Keffer | Product Manager

      2:00 PM- 3:00 PM

      • Wrap-up and Networking

      ** SEATING IS LIMITED, register below to save your seat.

    2. Date, Time & Location:

      Date & Time

      Tuesday, October 8th
      10:00 AM - 3:00 PM

      Location

      Siemens EDA
      46871 Bayside Parkway, Building B
      Fremont, CA, 94538
      +1 (510) 354-7400

      PLEASE NOTE:
      - Building B will show the address 46885 above the entry door (this is the correct building).
      - This event is in-person only -- there is no support for remote participation.

  2. Registration

    Thank you for registering, you will receive confirmation email shortly.