SystemVerilog Testbench Acceleration

In this time of complex user electronics, system companies need dramatic improvements in verification productivity. Functional verification is known to be a huge bottleneck for today's designs, and it is often mentioned that it takes up 60-70% of a design cycle. It is no surprise then that companies are constantly looking for ways to enhance verification productivity. Often this is by looking at adopting advanced verification methodologies like UVM to enhance their verification effort. It makes verification engineers more productive, basically allowing them to faster develop reusable testbenches and automated tests.

This track advocates that functional verification through modern testbenches paired with co-emulation enables further verification productivity improvements in terms of raw performance. Simulation paired with co-emulation will deliver dramatic speedup of execution of verification.

The Acceleration of SystemVerilog Testbenches with Co-Emulation track will give you the confidence required to start the process of investigating and creating a single testbench environment that can be used for both simulation as well as hardware-assisted acceleration and is approximately 1 hour of content, and is divided into four sessions.

The track is primarily aimed at existing SystemVerilog H/W engineers or managers who recognize they have a functional verification throughput problem but have little or no experience with using emulation as a means for accelerating SystemVerilog testbench environments, and may also be of interest to S/W engineers who demand earlier access to systems for S/W development.