Asynchronous_FIFO Design

class async_transaction #(
parameter int DATA_SIZE = 8,
parameter int ADDR_SIZE = 4);

//write transaction variables

rand bit w_enable;
rand bit\[DATA_SIZE-1:0\]wdata;

constraint c_wenable {soft w_enable dist {1:=80, 0:=20};}
constraint c_wdata {soft wdata inside {\[0:32\]};}

//read transaction variables

rand bit r_enable;

constraint c_renable {soft r_enable dist {1:=80, 0:=20};}

endclass:  async_transaction

The above is the transaction class for Asynchronous FIFO, I wanted to have one single transaction and one single driver and have added the both interface(write pointer and read pointer) signals in the single interface.

For Driver, I have used fork join_none and inside fork join_none, I have called drive_write and drive_read since both have independent clock domains.

drive_write is going to check the write reset and drive the write_enable, write_data to interface ports, and drive_read is going to check the read_reset and drive the read_enable to interface ports.

but when I call the mailbox.get(trans), the drive_write will get randomized read_enable
and drive_read will get randomized write_enable and wdata. I dont want the read pointer to see the randomized data of write_enable and wdata.

How can I build this?

You haven’t provided enough code or included crucial details to help you effectively. Additionally, since you’re not using UVM, it’s challenging to create the missing information. Could you please share more of the driver/monitor code?