Creating virtual function to get 'uvm_analysis_export' handles

UVM
1

I have following Systemverilog/UVM class structure. Is there a way to write a virtual function to get exp_axport and act_axport handles using sb_root handle?

virtual class sb_root extends uvm_scoreboard;
// common SB code here
endclass

virtual class sb_base #(type EXP_TXN_T = uvm_sequence_item,
	                    type ACT_TXN_T = uvm_sequence_item) extends sb_root;

	uvm_analysis_export #(EXP_TXN_T) exp_axport;
	uvm_analysis_export #(ACT_TXN_T) act_axport;
	
	virtual function void build_phase(uvm_phase phase);
		exp_axport = new("exp_axport", this);
		act_axport = new("act_axport", this);
	endfunction

	// other transaction type specific SB code here
endclass

class in_order_sb #(type EXP_TXN_T = uvm_sequence_item,
					type ACT_TXN_T = uvm_sequence_item
				   ) extends sb_base #(
				    .EXP_TXN_T(EXP_TXN_T),
					.ACT_TXN_T(ACT_TXN_T)
				   );
		// concrete SB code here		   
endclass

I’d like to create an associative array of scoreboards that stores all concrete in_order_sb handles with different parameter values.
e.g.

sb_root sb_map[string];
sb_map["AXI"] = axi_in_order_sb; // where axi_in_order_sb is defined as in_order_sb #(axi_item, axi_item)
sb_map["APB"] = apb_in_order_sb; // where apb_in_order_sb is defined as in_order_sb #(apb_item, apb_item)

If I can access uvm_analysis_exports using sb_root handle, then I can iterate through the sb_map and connect ports.