module tb;
event e1;
int a = 1;
initial begin : x
#1ns;
->e1;
a = 2;
end
initial begin : y
@e1;
$display("%0d", a);
end
endmodule
Hi @dave_59 ,
I have a few questions I’d like to ask you. After reading SystemVerilog LRM, I have some personal insights. For events within the same process (begin…end), they enter the Active queue in the order they occur; for events from different processes, they enter the Active queue in a random order.
So, in the example above, at 1 ns, the e1 is triggered. Theoretically, for the subsequent events in the initial blocks of x and y (a = 2; / $display(“%0d”, a);), the order in which they enter the Active queue is undetermined. Consequently, the value of a displayed at the end could be the default value 1 or 2. Is that correct?
BR