Suggestions for constraint on pattern occurrence

SystemVerilog
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1

Hi All,

I am trying a constraint to ensure that probability of pattern 4’b1101 occurring exactly once within 16-bit random variable is 70%.

Remaining 30% of the time we don’t care

Here is my attempt.

To ensure that the constraints achieve the intention I purposely created a conflict via in-line constraint ( ptrn[6:0] == 7’b1101101 which has 2 occurrence of 4’b1101 )

However to my surprise there is no constraint failure !!

As noted in the multi-line comment in the edalink I observe::

(1) When local variable a in post_randomize is ‘d64 i.e bit 6 is set I observe that ptrn[9:6] is 4’b1101. Along with the in-line constraint, 4’b1101 occurs atleast 3 times in ‘ptrn’

(2) When local variable a in post_randomize is ‘d4096 i.e MSb bit 12 is set I observe that ptrn[15:12] is 4’b1101. Along with the in-line constraint, 4’b1101 occurs atleast 3 times in ‘ptrn’

(3) When local variable a in post_randomize is ‘d8 i.e bit 3 is set I observe that ptrn[6:3] is 4’b1101. Along with the in-line constraint, 4’b1101 occurs atleast 2 times in ‘ptrn’

As per intention I should have observed 4’b1101 exactly once when ptrn_present is set

Seeking suggestions for the same

Thanks

2

There’s an issue with the implication constraint in the foreach loop. If the antecedent (LHS) is false, it doesn’t necessarily mean the consequent (RHS) must also be false. Below is the corrected constraint

constraint PATTERN { ptrn_present -> { // Below two constraints ensure that 4'b1101 occurs ONLY once !!
     ptrn_helper.sum() with (int'(item)) == 1;                                   
     foreach(ptrn_helper[i]) ptrn_helper[i] == (ptrn[i+:4] == 4'b1101) ;
                                         } 
                      }

Also, your ptrn_helper.or() constraint is redundant. It implies that the pattern must appear at least once, which is already covered by the constraint that it must appear exactly once.

3

Thanks Dave. I believe one could use equivalence ( ↔ ) operator as well within the foreach

4

Yes, using the equivalence operator would eliminate the need for parentheses because that operator has a lower precedence.

ptrn_helper[i] <-> ptrn[i+:4] == 4'b1101 ;