Hi Dave,
(1) As per 1800-2017, 18.5.4 Distribution, Syntax 18-3 says
dist_list ::= dist_item { , dist_item }
dist_item ::= value_range [ dist_weight ]
dist_weight ::=
:= expression
| :/ expression
expression [ dist { dist_list } ]
Annex A.8.3 explains
value_range ::= expression
| [ expression : expression ]
So essentially expression occurs in 3 places
expression1 dist { expression2 := expression3 }
LRM says
(a) The expression can be any intergral SystemVerilog expression
(b) A dist expression requires that the expression contain at least one rand variable
[Q1] What does expression in (a) and (b) point to ?
Is it expression1 / expression2 / expression3 or any of them ?
(2) Consider the following disturbution constraint for 4-bit random variable a
constraint d1 { (a > 11) dist { 1:/ 80, 0:/ 20 }; }
Result of (a > 11) is 0 or 1.
Essentially d1 constraints the probability of a greater than 11 to 0.8 whereas the probability of a <= 11 is 0.2
(3) Instead of d1 if I write the constraint as
constraint d2 { 1 dist { (a>11):/ 80, (a<=11):/ 20 }; }
[Q2] Isn’t d2 a valid disturbution constraint ? I observe compilation error with d2 on two EDA tools
[Q3] Is d2 equivalent to d1 ?
[Q4] How does a tool interpret d2 ?
Result of (a>11) / (a<=11) is 0/1.
As the lhs expression ( expression1 ) is 1, would the solver ensure that a is greater than 11, 80% of the time ?
(4) Is I were to write d1 as
constraint d1 { a dist { (a>11):/ 80, (a<=11):/ 20 }; }
I observe that a is either 0 or 1 ( although its a 4-bit variable )
This is due to result of (a>11) / (a<=11) being either 0 or 1.
[Q5] How is the distribution of a being 0 or 1 calculated in this case ?
One one of the EDA tool I observe a == 0 occurs much more than value of 1
Thanks