UVM and Emulation: How to Get Your Ultimate Testbench Acceleration Speed-up
This paper demystifies the performance of SystemVerilog and UVM testbenches when using an emulator for the purpose of hardware-assisted testbench acceleration. Architectural and modeling requirements are described, followed by a recommended systematic approach for maximizing overall testbench acceleration speed-up and achieving your ultimate performance expectations.
Power - Usage Shift Leads to Methodology Shift
In this paper, Veloce offers a unique and customized flow for SoC power exploration and analysis. Veloce Power Application is enabling a methodology shift in the way power measurements are done to address the new requirements due to usage shift. Chip designers do not need to rely on functional test benches and extrapolation techniques to come up with power number. The new flow enables booting OS, running live applications and run different functional use modes, scenario for generating accurate power data.
From Simulation to Emulation – A Fully Reusable UVM Framework
This paper introduces an acceleration-ready UVM framework and explains why it is needed, how to create it, and what its benefits are. By following the principles presented here, users will be able to write block-level UVM environments that can be reused directly in emulation. This approach has provided remarkable results in various customer environments, yielding a 50 to 5000X performance gain over pure simulation and significantly reducing testbench development time for emulation. With this new approach, users command a complete solution that can be used for block, subsystem, and system level verification.
Localized, System-Level Protocol Checks and Coverage Closure Using Veloce
Broadcom® recently developed a unified, scalable, verification methodology based on the Veloce® emulation platform. In order to test this new environment, they ran a test case, which proved that they can take assertions, compile them into Veloce, and verify that they fire accurately. In so doing, they were able to provide proof of concept for their primary goal: the creation of an internal flow to go from simulation verification with assertions to Veloce emulation with assertions.
Veloce System-Level Power Analysis and Verification
Power analysis and verification need to move to the system level, improving upon and extending the capabilities and scope of RTL and gate-level techniques. The performance, capacity, and flexibility of emulation platforms make them the ideal technology for system-level power analysis and verification. Veloce delivers unprecedented power verification and analysis capabilities. This paper shares how these capabilities are used and how they benefit the design and verification effort as well as the quality and power usage of complex SoC designs.
Virtual Devices for Protocol-Specific Host and Peripheral Interfaces
This paper provides a brief genealogy of virtual devices, describes their characteristics and benefits, and presents two design applications that demonstrate its utility and effectiveness.
Off to the Races with Your Accelerated SystemVerilog Testbench
This document describes a methodology for writing SystemVerilog and OVM or UVM testbenches that can be used not only for software simulation, but especially for hardware-assisted acceleration using Mentor's Veloce TBX solution. The methodology presented herein promotes the co-emulation (also known as co-modeling) approach and aims to maximize reuse between pure simulation-based verification and hardware-assisted acceleration.
An Acceleratable OVM Methodology Based on SCE-MI 2
This paper proposes a methodology update on OVM to support transaction based acceleration. The methodology enables transaction based verification of an OVM testbench using SCE-MI 2 based co-emulation modeling techniques to provide the much needed execution efficiency.
The Target Platform Methodology for Hw/SW Debugging Before Silicon
As designers seek to reduce their risk and increase their design confidence, the pressures result in demanding verification needs such as high-performance verification acceleration, 100 percent observability, and full testing coverage.