Featured Acceleration Verification Horizons Articles
- Why Hardware Emulation Is Necessary to Verify Deep Learning Designs
- Three Main Components to Look for in Your Emulation Platform
- Emulation – A Job Management Strategy to Maximize Use
- 24 x 7 Productivity: Veloce® Enterprise Server App Does the Job
- Accelerating Networking Products to Market
- Hardware Emulation: Three Decades of Evolution—Part III
- Hardware Emulation: Three Decades of Evolution – Part II
- Hardware Emulation: Three Decades of Evolution
- Emulation Based Approach to ISO 26262 Compliant Processors Design
- Optimizing Emulator Utilization
- Simulation + Emulation = Verification Success
- Bringing Verification and Validation under One Umbrella
- Virtualization Delivers Total Verification of SoC Hardware, Software, and Interfaces
Featured Acceleration White Papers
- From Simulation to Emulation – A Fully Reusable UVM Framework
- UVM and Emulation: How to Get Your Ultimate Testbench Acceleration Speed-up
- Parameters, UVM, Coverage & Emulation – Take Two and Call Me in the Morning
- UVM and Emulation: How to Get Your Ultimate Testbench Acceleration Speed-up
- Off to the Races with Your Accelerated SystemVerilog Testbench
- Optimizing Emulator Utilization
- Power - Usage Shift Leads to Methodology Shift
- Exploring New Uses for the Veloce DFT App, Fault Coverage and Power Analysis
- Localized, System-Level Protocol Checks and Coverage Closure Using Veloce
- Veloce System-Level Power Analysis and Verification
- Virtual Devices for Protocol-Specific Host and Peripheral Interfaces
Featured Acceleration On-Demand Technical Sessions
- Creating UVM Testbenches for Simulation & Emulation Platform Portability
- UVM and Emulation: Easing the Path to Advanced Verification and Analysis
- Full SoC Emulation from Device Drivers to Peripheral Interfaces
- Methodology for Hardware-Assisted Acceleration of OVM and UVM Testbenches
- Off-line Debug of Multi-Core SoCs with Veloce Emulation
- Making Hardware/Software Co-Verification Easier for ARM Cortex™-A Series Processor-based Designs
Scalable Verification Platforms with Capacities from 16M to 2B gates
The Veloce® Emulation Platform dramatically reduces risk in the verification of today’s complex SoCs and is a core technology in the Mentor Enterprise Verification Platform™ (EVP).
The Veloce emulation platform combines a unique hardware architecture, innovative operating system, specialized applications, and versatile peripheral solutions to deliver a comprehensive and flexible high-speed, high-capacity verification environment. Veloce accelerates simulation and provides uncompromised visibility and debug.