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Acceleration

Acceleration

Acceleration are techniques that are used to address performance shortcomings of traditional simulation. For example, the design model (i.e., DUT) can be mapped into a hardware accelerator and run much faster during verification, while the testbench continues to run in simulation on a workstation. In this section of the Verification Academy, we focus on building verification acceleration skills.

Acceleration Courses

SystemVerilog Testbench Acceleration

Acceleration of SystemVerilog Testbenches with Co-Emulation | Subject Matter Expert - Hans van der Schoot | Acceleration Topic

This course will give you the confidence required to start the process of investigating and creating a single testbench environment for both simulation and hardware-assisted acceleration.

Testbench Co-Emulation: SystemC & TLM-2.0

Acceleration of SystemC and TLM-2.0 Testbenches with Co-Emulation Course | Subject Matter Expert - John Stickley | Acceleration Topic

This course advocates that functional verification through modern SystemC testbenches paired with co-emulation enables further verification productivity improvements.

Acceleration Resources

Virtualization Delivers Total Verification of SoC Hardware, Software, and Interfaces

With the majority of designs today containing one or more embedded processors, the verification landscape is transforming as more companies grapple with the limitations of traditional verification tools. Comprehensive verification of multi-core SoCs cannot be accomplished without including the software that will run on the hardware.
Horizons Article

A Methodology for Hardware-Assisted Acceleration of OVM and UVM Testbenches

A methodology is presented for writing modern SystemVerilog testbenches that can be used not only for software simulation, but especially for hardware-assisted acceleration.
Horizons Article

Collaborative Verification of Third-Party IP in Early Adopter SoCs

The presence of ARM® and other third-party IP in system-on-chip(SoC) designs has become ubiquitous, simplifying design while complicating verification.
Horizons Article

Mentor Graphics Launches Next Generation Veloce2 Emulation Platform with VirtuaLAB Capabilities

The Veloce VirtuaLAB builds on the emulator’s ability to run hardware designs written in RTL at megahertz speeds. By integrating RTL models of key peripherals like USB, Ethernet, PCIe and the like, the Veloce VirtuaLAB is able to create a full target environment that allows developers to validate both the hardware and embedded software, before any hardware is manufactured.
Press Release

Altera Adopts the Mentor Graphics Veloce Hardware Emulator to Accelerate Time-to-Market for their Next-Gen Products

Altera chose the Veloce platform due to its high runtime performance, fast compiler technology, ease-of-use, excellent debug capabilities, and the ability to mix transaction-based acceleration and traditional in-circuit emulation (ICE) modes of operation.
Press Release

Mentor Graphics Delivers Emulation-Ready Transactors for the Accelerated Verification of SoCs

The Veloce transactors enable the use of stimuli generated by modern simulation testbenches, including SystemVerilog/OVM and UVM, SystemC, and ‘C’- based environments, and apply them to the design-under-test (DUT) running in the Veloce hardware.
Press Release

Virtual Devices for Protocol-Specific Host and Peripheral Interfaces

This paper provides a brief genealogy of virtual devices, describes their characteristics and benefits, and presents two design applications that demonstrate its utility and effectiveness.
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Off to the Races with Your Accelerated SystemVerilog Testbench

This document describes a methodology for writing SystemVerilog and OVM or UVM testbenches that can be used not only for software simulation, but especially for hardware-assisted acceleration using Mentor's Veloce TBX solution.
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An Acceleratable OVM Methodology Based on SCE-MI 2

This paper proposes a methodology update on OVM to support transaction based acceleration. The methodology enables transaction based verification of an OVM testbench using SCE-MI 2 based co-emulation modeling techniques to provide the much needed execution efficiency.
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The Target Platform Methodology for Hw/SW Debugging Before Silicon

As designers seek to reduce their risk and increase their design confidence, the pressures result in demanding verification needs such as high-performance verification acceleration, 100 percent observability, and full testing coverage.
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A Methodology for Hardware-Assisted Acceleration of OVM and UVM Testbenches

It's often desirable to co-simulate abstract high-level descriptions with RTL blocks. This eliminates the task of creating ESL models for legacy RTL that lies outside the design exploration space and is not subject to change.
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Off-line Debug of Multi-Core SoCs with Veloce Emulation

This presentation and demonstration will introduce a solution to reduce debug time and effort required to ensure that SoC firmware and device drivers interact seamlessly with design hardware.
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Making Hardware/Software Co-Verification Easier for ARM Cortex™-A Series Processor-based Designs

This session will cover how Questa Codelink automates the debugging process for multi-core designs based on the ARM Cortex-A series processors.
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