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  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum

    • SystemVerilog Forum

      • Active Questions
      • Solutions
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      • No Replies
      • Search
      • SystemVerilog Forum

    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • The Digital Twin: An Aerospace and Defense Revolution - March 9th
      • VIP solutions for Protocol and Memory Verification  - March 11th
      • Advance your Designs with Advances in CDC and RDC - March 23rd
      • Webinar Calendar

    • On Demand Seminars

      • The ABC of Formal Verification
      • I'm Excited About Formal...
      • 2020 Functional Verification Study
      • All On-Demand Seminars

    • Recording Archive

      • Improving Your SystemVerilog & UVM Skills
      • Should I Kill My Formal Run?
      • Visualizer Debug Environment
      • All Recordings

    • Conferences

      • DVCon 2020
      • DAC 2019
      • All Conferences

    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Academy Newsletter
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - March 2021
      • Verification Horizons - November 2020
      • Verification Horizons - July 2020
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa® & ModelSim®
      • Questa® inFact
      • Functional Verification Library
  • Home
  • Topics
  • Acceleration

Acceleration

Acceleration

Acceleration are techniques that are used to address performance shortcomings of traditional simulation. For example, the design model (i.e., DUT) can be mapped into a hardware accelerator and run much faster during verification, while the testbench continues to run in simulation on a workstation. In this section of the Verification Academy, we focus on building verification acceleration skills.

Acceleration Courses

Testbench Co-Emulation: SystemC & TLM-2.0

Acceleration of SystemC and TLM-2.0 Testbenches with Co-Emulation Course | Subject Matter Expert - John Stickley | Acceleration Topic

This course advocates that functional verification through modern SystemC testbenches paired with co-emulation enables further verification productivity improvements.

SystemVerilog Testbench Acceleration

SystemVerilog Testbenches Acceleration | Subject Matter Expert - Hans van der Schoot | Acceleration Topic

This course will give you the confidence required to start the process of investigating and creating a single testbench environment for both simulation and hardware-assisted acceleration.

Acceleration Resources

  • Articles
  • White Papers
  • On-Demand
  • Success Stories
  • Product Information

Featured Acceleration Verification Horizons Articles

  • Why Hardware Emulation Is Necessary to Verify Deep Learning Designs
  • Three Main Components to Look for in Your Emulation Platform
  • Emulation – A Job Management Strategy to Maximize Use
  • 24 x 7 Productivity: Veloce® Enterprise Server App Does the Job
  • Accelerating Networking Products to Market
  • Hardware Emulation: Three Decades of Evolution—Part III
  • Hardware Emulation: Three Decades of Evolution – Part II
  • Hardware Emulation: Three Decades of Evolution
  • Emulation Based Approach to ISO 26262 Compliant Processors Design
  • Optimizing Emulator Utilization
  • Simulation + Emulation = Verification Success
  • Bringing Verification and Validation under One Umbrella
  • Virtualization Delivers Total Verification of SoC Hardware, Software, and Interfaces

Featured Acceleration White Papers

  • From Simulation to Emulation – A Fully Reusable UVM Framework
  • UVM and Emulation: How to Get Your Ultimate Testbench Acceleration Speed-up
  • Parameters, UVM, Coverage & Emulation – Take Two and Call Me in the Morning
  • UVM and Emulation: How to Get Your Ultimate Testbench Acceleration Speed-up
  • Off to the Races with Your Accelerated SystemVerilog Testbench
  • Optimizing Emulator Utilization
  • Power - Usage Shift Leads to Methodology Shift
  • Exploring New Uses for the Veloce DFT App, Fault Coverage and Power Analysis
  • Localized, System-Level Protocol Checks and Coverage Closure Using Veloce
  • Veloce System-Level Power Analysis and Verification
  • Virtual Devices for Protocol-Specific Host and Peripheral Interfaces

Featured Acceleration On-Demand Technical Sessions

  • Creating UVM Testbenches for Simulation & Emulation Platform Portability
  • UVM and Emulation: Easing the Path to Advanced Verification and Analysis
  • Full SoC Emulation from Device Drivers to Peripheral Interfaces
  • Methodology for Hardware-Assisted Acceleration of OVM and UVM Testbenches
  • Off-line Debug of Multi-Core SoCs with Veloce Emulation
  • Making Hardware/Software Co-Verification Easier for ARM Cortex™-A Series Processor-based Designs

Featured Acceleration Success Stories

  • ARM® Uses Veloce2 To Verify State-of-the-Art Chips And Software
  • Marvell Overcomes Standard Interface And SoC Challenges With Veloce2
  • Cavium’s Success With Veloce, TBX And EPGM Virtual Tester
  • Veloce Speeds Debug of Ostendo Mobile 3D Projector on Chip

Scalable Verification Platforms with Capacities from 16M to 2B gates

The Veloce® Emulation Platform dramatically reduces risk in the verification of today’s complex SoCs and is a core technology in the Mentor Enterprise Verification Platform™ (EVP).

The Veloce emulation platform combines a unique hardware architecture, innovative operating system, specialized applications, and versatile peripheral solutions to deliver a comprehensive and flexible high-speed, high-capacity verification environment. Veloce accelerates simulation and provides uncompromised visibility and debug.

Learn more | Datasheet

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