Parameterized interface in systemverilog design

SystemVerilog
1

Hi,
I am trying to find an emulation friendly way of importing a typedef from interface to a module.
Tried as suggested in the post: parameterized struct in systemverilog design | Verification Academy

typedef p1.stage_t stage_t; // “imports” type into module

this works in the sim env but in the emulation env it is not supported, I get the following issue:
Hierarchical reference in typedef declaration (…) to data-type import from interface is not yet supported

2

In reply to skroot:

You will need to contact your tool vendor for a “not yet supported” issue