module dummy #(
parameter ARR_SZ,
parameter bit[INT_B-1:0] VAR_A[ARR_SZ ? ARR_SZ : 1], parameter bit[
INT_B-1:0] VAR_B[ARR_SZ ? ARR_SZ : 1],
) (
.
.
.
);
import "DPI-C" context task import_func(
input bit[`INT_B-1:0] p_var_a[ARR_SZ ? ARR_SZ : 1],
input bit[`INT_B-1:0] p_var_b[ARR_SZ ? ARR_SZ : 1],
input bit[`INT_B-1:0] p_arr_sz
);
initial begin
import_func(VAR_A, VAR_B, ARR_SZ);
end
endmodule
for the above dpi function ‘import_func’ what will be the corresponding c prototype and how can I parse over these array of vector in c. Thank you
You can make DPI much simpler by using C compatible types instead of packed arrays. Also, import as function
not a task
unless you are planning to have the imported C routine call an SystemVerilog exported task.
If you were to change the imported function to
import "DPI-C" context function void import_func(
input bit[`INT_B-1:0] p_var_a[ARR_SZ ? ARR_SZ : 1],
input int p_var_b[ARR_SZ ? ARR_SZ : 1],
input int p_arr_sz
);
It’s C prototype would be
void import_func(
const svBitVecVal* p_var_a,
const int* p_var_b,
int p_arr_sz);
Some tools like Questa have an option to generate these prototypes automatically during compilation so you don’t have to guess and get runtime fatal errors.
Once you start passing packed arrays(single or multi-dimensional), you need to use helper functions to access the individual bits. See Annex H.11.5 Utility functions for working with the canonical representation in the IEEE 1800-2017 LRM.
Hey @dave_59 , this is to be synthasizable verilog and the emulator I am working on requires the DPI to be a task for passing packed arrays.
Thanks, I am able to get it working with the above dpi prototype and utility functions.