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Israel Static & Formal Tech Day (7)

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VA Live 2023 - Huntsville (7)

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March 2016 - Volume 12 Issue 1 (5)

Mixed-Signal Verification (5)

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VA Live 2023 - Westford (5)

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March 2015 - Volume 11 Issue 1 (4)

March 2024 - Volume 20 Issue 1 (4)

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PCIe Gen 6 (4)

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UPF 4.0 (4)

VA Live 2023 - Austin (4)

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VA Live 2024 - Westford (4)

VA Live 2025 - Huntsville (4)

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Waivers (4)

Whats New in Functional Verification (4)

Wilson Research Group (4)

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ATPG (3)

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December 2017 - Volume 13 Issue 3 (3)

Design Cycle (3)

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Front and Back Door (3)

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HLV (3)

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High-Speed (3)

IP Integration (3)

IP Security (3)

JEDEC (3)

July 2022 - Volume 18 Issue 2 (3)

June 2015 - Volume 11 Issue 2 (3)

March 2020 - Volume 16 Issue 1 (3)

March 2021 - Volume 17 Issue 1 (3)

Memory Models (3)

Multi-Core Architectures (3)

Namespaces (3)

October 2012 - Volume 8 Issue 3 (3)

PCIe Gen 7 (3)

Parallel Simulation (3)

Power Architecture (3)

Processor Core Verification (3)

Protocol Checkers (3)

Python (3)

QFL (3)

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SSD (3)

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Static Checks (3)

System Level (3)

Tcl/Tk (3)

Transfer Protocols (3)

Trends (3)

Trust Verification (3)

UALink (3)

UVMC 2.3.3 (3)

UVMC 2.3.4 (3)

Unified Coverage Database (3)

VA Live 2019 - Westford (3)

VA Live 2024 - Austin (3)

VA Live 2024 - Fremont (3)

Validation (3)

Variable (3)

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Virtual Interface (3)

osmosis 2023 A&D (3)

2D/3D (2)

5G (2)

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ASIL-C (2)

Abstract Specification (2)

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C (2)

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CHI (2)

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Certification (2)

Channel Detection (2)

Clock Bridge (2)

Clocking (2)

Clocking Verification Challenges (2)

Configuration Database (2)

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Critical Storage (2)

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Cutpoint (2)

DPPM (2)

DVCON 2021 (2)

DVFS (2)

Data Corruption (2)

Data Encryption (2)

Data Link (2)

Data Types (2)

December 2019 - Volume 15 Issue 3 (2)

December 2022 - Volume 18 Issue 3 (2)

Design Checking (2)

Design for Safety (2)

Digital Signal Processing (2)

Distributed Resource Management (2)

Elements List (2)

Ethernet (2)

FIT Rate (2)

Fabric (2)

Fault Detection (2)

Fault Model (2)

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Formal Simulation (2)

GLS (2)

GOMACTech (2)

Governance (2)

Graph-Based Stimulus (2)

Hallucination (2)

Hardening (2)

Hardware Designs (2)

Hardware-Assisted Verification (2)

Heterogeneous (2)

IC Design (2)

IEEE (2)

IEEE 754 (2)

IP-XACT (2)

ISA (2)

Illegal Bins (2)

Implementation Model (2)

Implicit/Explicit (2)

In-Circuit Simulation (2)

Instance Mapping (2)

Instantiate (2)

Intelligent Integration (2)

Interconnect Signals (2)

Jittering (2)

June 2013 - Volume 9 Issue 2 (2)

June 2014 - Volume 10 Issue 2 (2)

LVS (2)

Level-shifter (2)

Lockstep (2)

Loggers (2)

Logic Cone (2)

MIPI (2)

Machine Readable Specification (2)

March 2014 - Volume 10 Issue 1 (2)

March 2017 - Volume 13 Issue 1 (2)

March 2022 - Volume 18 Issue 1 (2)

Metastable (2)

Metric Validation (2)

Mixed-Signal Design (2)

Modules (2)

Monitor (2)

Multi-Language Environment (2)

Non-Determinism (2)

Object Oriented Programming (2)

October 2013 - Volume 9 Issue 3 (2)

OnChip (2)

Open Architecture (2)

PAM4 (2)

PCI-SIG (2)

PMHF (2)

Parameter (2)

Parameter-to-Signal (2)

Parameterized Tests (2)

Partitioning (2)

Pattern Splitting (2)

Point-to-Point Connections (2)

Polymorphism (2)

Post-silicon Debug (2)

Power Profiling (2)

Power Reduction (2)

Precedence (2)

Profiling (2)

Property Analysis (2)

QCX (2)

Questa Design Solutions (2)

RDC Analysis (2)

RDC Violations (2)

Re-targeting (2)

Reference Model (2)

Reset Handling (2)

Reset Value (2)

Retargeting Flow (2)

Runtime (2)

SFV (2)

SLM (2)

SPFM (2)

Scoreboard (2)

Security Vulnerabilities (2)

Shift Left (2)

Sign-Off Methodology (2)

Silicon Lifecycle Management (2)

Software-Driven Verification (2)

Spice (2)

Split Transactor (2)

State Preservation (2)

Stimulus Free Verification (2)

Strategy (2)

Sub-system (2)

Substrate (2)

Successive Refinement (2)

Supply Chain (2)

Synthesizable (2)

System-in-Package (2)

TLM FIFOS (2)

Test Environment (2)

Test Generation (2)

Test Planning (2)

Test Ranking (2)

Testing Strategies (2)

Time Cone (2)

Transitive (2)

UPF 2.0 (2)

UPF 3.0 (2)

USB (2)

UVMC 2.3.0 (2)

UVMC 2.3.1 (2)

UVMC 2.3.2 (2)

Ultra Accelerator Link (2)

Universal Approximation (2)

Unreachability (2)

VRM (2)

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Virtual Prototyping (2)

X-Mitigation (2)

X-Pessimism (2)

X-State (2)

osmosis 2024 A&D (2)

$display (1)

2.5D (1)

2.5DIC (1)

3PIP (1)

AHB (1)

AHB-Lite (1)

AOP (1)

APB (1)

API (1)

AXI (1)

Active Driver Tracing (1)

Address Space Management (1)

Adoption Trends (1)

Advance Your Verification Methodology (1)

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Agent (1)

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Alternate Routing ID (1)

Analysis Components (1)

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Autonomous Vehicles (1)

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Back Pointers (1)

Batch and Debug (1)

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Block to Chip (1)

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Build Phase (1)

C-PHY (1)

CMA (1)

COTS (1)

CSD (1)

CSI (1)

CSI-2 (1)

CXL (1)

Case Statements (1)

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Clock Cycle (1)

Cloud Computing (1)

Cloud-Based Environment (1)

Code Example (1)

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Code Quality (1)

Combinational Loops (1)

Component Measurement and Authentication (1)

Compute Express Link (1)

Config_db (1)

Connected Verification (1)

Continuous Integration System (1)

Control Paths (1)

Control Points (1)

Controller Area Network (1)

Counterexample (1)

Cover Property (1)

Coverage Achievement (1)

Coverage Models (1)

D-PHY (1)

DVCon Europe (1)

Debug Methodology (1)

Design Complexity (1)

Design Constraints (1)

Design Specification (1)

Design.bin (1)

Determinism (1)

Deterministic Test (1)

DisplayPort (1)

Dual Domains (1)

Dynamic CDC (1)

ED-80 (1)

EMC (1)

Electronic Design Integration (1)

Elliptic Curve (1)

Embedded Analytics (1)

Embedded Software (1)

Emerging Trends (1)

Enterprise Debug and Analysis (1)

Execution Trace (1)

Factory (1)

Fault Coverage (1)

February 2013 - Volume 9 Issue 1 (1)

February 2019 - Volume 15 Issue 1 (1)

Fibre Channel (1)

Flash (1)

Flip-Flop (1)

Floating-Point Hardware (1)

Formal Test Planning (1)

Formal Verification Apps (1)

Functional Monitoring (1)

GPU (1)

Generation (1)

Golden Model (1)

HDMI (1)

HSI (1)

HYCON (1)

Hierarchical Components (1)

Hierarchical Sequences (1)

Host Processor (1)

IC/ASIC (1)

IDE (1)

IEC 62304 (1)

IP Integrator (1)

IP Quality (1)

In-Circuit Emulation (1)

In-System Test (1)

Instance (1)

Integer (1)

Integration Level (1)

Interrupts (1)

Japanese (1)

July 2020 - Volume 16 Issue 2 (1)

July 2023 - Volume 19 Issue 2 (1)

June 2012 - Volume 8 Issue 2 (1)

June 2016 - Volume 12 Issue 2 (1)

June 2017 - Volume 13 Issue 2 (1)

June 2018 - Volume 14 Issue 2 (1)

June 2019 - Volume 15 Issue 2 (1)

LSTM (1)

Logic Faults (1)

Low Latency (1)

MCPs (1)

MUX (1)

March 2018 - Volume 14 Issue 1 (1)

March 2023 - Volume 19 Issue 1 (1)

Marvell (1)

Mathworks (1)

Measurement (1)

Memory BIST (1)

Memory Debug (1)

Memory Usage (1)

Model-Based Design (1)

Multi-Cycle Paths (1)

NAND (1)

NLP (1)

NRRs (1)

Non-Resettable Registers (1)

Non-Trivial Bug Escapes (1)

November 2015 - Volume 11 Issue 3 (1)

November 2016 - Volume 12 Issue 3 (1)

November 2018 - Volume 14 Issue 3 (1)

November 2020 - Volume 16 Issue 3 (1)

Objectives (1)

Objects (1)

Observer (1)

PCIe Gen 4 (1)

PHY (1)

Partitioned Compile (1)

Phases (1)

Phrase Configuration (1)

Portability (1)

Power Gating (1)

Pre-Silicon (1)

Productivity Gap (1)

Property Editor (1)

Prototyping (1)

QEMU (1)

QOS Processor (1)

RAM (1)

RDC Methodology (1)

RDMA (1)

RISC-V Verification Interface (1)

RNG (1)

RTL Emulation (1)

RTL-Aware Design (1)

Re-Spins (1)

Receiver (1)

Recording (1)

Recurrent Neural Networks (1)

Release Notes (1)

Repair Architecture (1)

Reporting (1)

Reset Environment (1)

Reset Tree (1)

Respins (1)

Root Complex (1)

Run Monitor (1)

SA-EDI (1)

SATA (1)

SCE-MI (1)

SOTIF (1)

SPDM (1)

SPI (1)

SafeSPI (1)

Safety Monitoring (1)

Scenario Generation (1)

Security Asset (1)

Security Coverage (1)

Security Protocol and Data Model (1)

Sequencer (1)

Sequential Errors (1)

Sequential Optimization (1)

Signal Processing Domain (1)

Single Root-IO Virtualization (1)

Singleton (1)

Softmodel (1)

Software Layers (1)

Spiral Refinement (1)

Static CDC (1)

Static Formal (1)

Static RDC (1)

Sub-Module (1)

Subscriber (1)

Supply Set (1)

Systemic Faults (1)

TBX (1)

TDISP (1)

TPU (1)

Test Compression (1)

Test Coverage (1)

Tool Confidence Level (1)

Tool Detection (1)

Tool Impact (1)

Trace Depth (1)

Transaction Layer (1)

Transactional Assertions (1)

Transactors (1)

Transmitter IP (1)

Tunneling (1)

UCIS (1)

UEC (1)

UPF 3.1 (1)

USB 3.0 (1)

USB 3.1 (1)

UVM Simulation (1)

UVM-MS (1)

UVMC 2.1.4 (1)

UVMC 2.2 (1)

UVVM (1)

Unary (1)

Unidirectional (1)

Use Models (1)

VA Live 2023 - El Segundo (1)

VC File (1)

VCMs (1)

VIP - 3.1 (1)

Values (1)

VbyOne (1)

Vectors (1)

Verbose (1)

Verbosity (1)

Verification Component (1)

Verification Run Manager (1)

Virtual Equivalence (1)

Virtual Methods (1)

WRG (1)

Wall-Clock Run-Time (1)

X-Optimism (1)

XML (1)

YAML (1)

eFuse (1)

Show Less

February 2026

AI Assisted FPU Verification Using Questa One SFV
Formal Verification Feb 25, 2026 Gerardo Nahum Webinar
Verification Academy Live: El Segundo Topgolf
Verification Academy Live Feb 24, 2026 Joe Hupcey Seminar
Verification Academy Live: Austin Topgolf
Verification Academy Live Feb 19, 2026 Joe Hupcey Seminar
Securing Next-Generation Interconnects: PCIe® Gen7 Security Verification
Verification IP Feb 18, 2026 Jalaj Gupta Webinar
Verification Academy Live in Silicon Valley - Avery Verification IP for AI/ML/HPC
Verification Academy Live Feb 04, 2026 Joe Hupcey Seminar

January 2026

New Innovative Way to Functionally Verify Heterogeneous 2D/3D Package Connectivity
Formal Verification Jan 16, 2026 Jin Hou pdf
New Innovative Way to Functionally Verify Heterogeneous 2D/3D Package Connectivity
Formal Verification Jan 16, 2026 Jin Hou Paper

December 2025

Formal Verification of Synthesizable C++/SystemC Designs
Formal Verification Dec 12, 2025 Vlada Kalinic pdf
Formal Verification of Synthesizable C++/SystemC Designs
Formal Verification Dec 12, 2025 Vlada Kalinic Paper
Aerospace & Defense
Functional Safety Dec 03, 2025 Todd Holbrook Reference

November 2025

HLV: Formal Verification of Synthesizable C++/SystemC Designs
Formal Verification Nov 05, 2025 Vlada Kalinic Webinar
HLV: Formal Verification of Synthesizable C++/SystemC Designs
Formal Verification Nov 05, 2025 Vlada Kalinic pdf

October 2025

Boosting Verification of an IEEE Compliant FPU with Formal and AI Capabilities
Machine Learning Oct 16, 2025 Zvi Ben Yosef - Nextsilicon mp4
Boosting Verification of an IEEE Compliant FPU with Formal and AI Capabilities
Machine Learning Oct 16, 2025 Zvi Ben Yosef - Nextsilicon pdf
Combining Performance and Formal Security Guarantees for Hardware Accelerators
Formal Verification Oct 16, 2025 Lucas Deutschmann - Rptu University Kaiserslautern-Landau pdf
Combining Performance and Formal Security Guarantees for Hardware Accelerators
Formal Verification Oct 16, 2025 Lucas Deutschmann - Rptu University Kaiserslautern-Landau mp4
Ground Truth in the Age of AI: Abstract Models as the Anchor of Verification
Machine Learning Oct 16, 2025 Tobias Ludwig - Lubis Eda pdf
Ground Truth in the Age of AI: Abstract Models as the Anchor of Verification
Machine Learning Oct 16, 2025 Tobias Ludwig - Lubis Eda mp4
Adaptable FWHW Formal Co-Verification of SoC RISC-V Components
Formal Verification Oct 16, 2025 Bryan Olmos - Infineon mp4
Adaptable FWHW Formal Co-Verification of SoC RISC-V Components
Formal Verification Oct 16, 2025 Bryan Olmos - Infineon pdf
Formally Verifying Security Properties of CHERI Hardware and Software
Formal Verification Oct 16, 2025 Thomas Bauereiss - University Of Cambridge mp3
Formally Verifying Security Properties of CHERI Hardware and Software
Formal Verification Oct 16, 2025 Thomas Bauereiss - University Of Cambridge pdf
Harnessing AI for Real-world Hardware Verification
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BUGGED OUT Podcast

Every chip has bugs — the real question is how fast you can find and fix them.

VA Live Silicon Valley

Wednesday, Feb 04th-9:30 AM PST

Avery Verification IP for AI/ML/HPC | Santa Clara, CA

Coverage Analysis Webinar

Thursday, Feb 05th-8:00 AM PST

Close Coverage Faster with Questa One Sim's Unreachability Analysis

Low Power Webinar

Wednesday, Feb 11th-12:00 PM PST

Don’t Miss CDC Bugs in Low Power Designs!: Formal Meets Power Aware CDC

PCIe® Gen7 Webinar

Wednesday, Feb 18th-10:00 AM PST

Securing Next-Generation Interconnects: PCIe® Gen7 Security Verification

VA Live Austin

Thursday, Feb 19th-7:30 AM PST

Discussing the AI/ML paradigm shift across the industry.

VA Live El Segundo

Tuesday, Feb 24th-9:30 AM PST

Discussing the latest advancements in RTL simulation.

FPU Verification Webinar

Wednesday, Feb 25th-8:00 AM PST

AI Assisted FPU Verification Using Questa One SFV

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Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

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