Optimizing Functional Fault Grading Flow for Memory Designs with Questa One Sim FX
In this User2User Europe session, you will learn about an advanced fault simulation flow for memory design (DRAM). Accomplishing bridges the gap between TR-level design complexity and high-performance gate-level fault grading using Questa One Sim FX. To overcome various challenges and accelerate simulation speed, we implemented a strategic Design Pruning and diverse optimization techniques. we successfully mitigated the runtime bottlenecks typically associated with exhaustive fault analysis.
