PCIe 8.0 over UCIe 3.0: Bringing a Proven Protocol into the Chiplet Era

For PCIe 8.0, this approach enables high bandwidth with better transport efficiency, enhanced modularity, and stronger scalability for AI, HPC, and heterogeneous compute systems.

For more than two decades, PCI Express (PCIe) has been the industry’s default interconnect for connecting processors, accelerators, storage, networking, andmemory subsystems. Since its inception in 2003, its value lies in its ever-increasing bandwidth and the combination of transaction semantics, software compatibility, ecosystem maturity, and interoperability that has made PCIe the backbone of modern compute platforms.

That value remains highly relevant as architecture moves from monolithic SoCs to chiplet-based designs. In a chiplet system, functions that once resided on a single die are partitioned across multiple dies within the same package, resulting in significantly improved manufacturing yield. But this shift also changes the physical interconnect problem as board-oriented assumptions that shaped conventional PCIe implementations are no longer ideal for short-reach, in-package communication.

This is where UCIe 3.0 becomes strategically important. UCIe standardizes die-to-die communication within a package and allows PCIe traffic to traverse chiplet boundaries with seamless interoperability over standardized interconnects. In effect, PCIe continues to provide the upper-layer protocol model, while UCIe supplies the optimized die-to-die transport and physical infrastructure needed for chiplet integration. For PCIe 8.0, this approach enables high bandwidth with better transport efficiency, enhanced modularity, and stronger scalability for AI, HPC, and heterogeneous compute systems.

What UCIe solves for PCIe

UCIe replaces the conventional PCIe PHY at the die-to-die boundary with the die-to-die (D2D) adapter and logical PHY, which are optimized for the system-in-package environment. Figure 1 illustrates this partitioning, where root complex and endpoint die retain their PCIe transaction layer and data link layer (DLL) while UCIe sideband and mainband links provide the die-to-die transport.

^{Figure 1. Root complex and endpoint dies linked via UCIe}