Automated Requirement Driven, SystemVerilog-based Verification Workflow for Mixed-Signal ASICs
In this User2User Europe session, you will be introduced to a FuSa workflow connecting ASIC development using Siemens Polarion requirements management with advanced SystemVerilog verification and chip-level mixed-signal validation. This approach ensures robust sign-off and coverage across analog and digital domains while maintaining strict design-to-requirement alignment by integrating specifications and verification items into VIP-based SystemVerilog testbenches and assertions.
