Verification IP Webinar

Wednesday, May 20th-8:00 AM PDT

Breaking Bandwidth Barriers in the AI Era: Scaling PCIe with Retimers and Optical Innovation

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Wednesday, Jun 03rd-8:00 AM PDT

AI for Early SoC Security Verification

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BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

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DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

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DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

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Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

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SIEMENS Verification Academy

From Apps to Orchestration: Agentic AI for Autonomous RTL Signoff with Questa One Agentic Toolkit

Join us to explore how this open, MCP-based architecture enables seamless integration with GitHub Copilot, Claude Code, Cursor, Cline, or Siemens Fuse, supports vendor-neutral AI models (OpenAI, Anthropic, NVIDIA Nemotron), and delivers autonomous RTL signoff that liberates engineers from repetitive tasks while preserving human oversight for trusted design closure available for deployment today.

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