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Without Objection: Touring the uvm_objection Implementation - Uses and Improvements

Paper - May 13, 2024 Rich Edelman

The SystemVerilog UVM implements a class named uvm_objection. An objection is used to guard code that “isn't done yet.” For example, an objection can prevent a process from finishing until some other process agrees. uvm_objections are sometimes overused and are always misunderstood. This paper will explain the implementations, share uses and provide some alternative solutions that are easier to understand, simpler to use, and work transparently.
On Analysis of RDC Issues for Identifying Reset Tree Design Bugs and Further Strategies for Noise Reduction

Paper - May 10, 2024 Farhad Ahmed

Reset tree checks should be viewed thoroughly before RDC analysis. Static verification tools have many checks for reset tree analysis. This paper discusses the usage of non-resettable registers (NRRs) in reset paths. NRRs can cause metastability in the reset paths and hence thorough verification is a must. The paper discusses reduction of false failure reporting noise strategies in RDC analysis. Stable paths and functional false paths are the focus of the discussion in noise reduction.
On Analysis of RDC Issues for Identifying Reset Tree Design Bugs and Further Strategies for Noise Reduction

Resource (Paper (.PDF)) - May 10, 2024 Farhad Ahmed

This paper discusses reduction of false failure reporting noise strategies in RDC analysis. Stable paths and functional false paths are the focus of the discussion in noise reduction, and we discuss various scenarios and how static verification tool should report these paths.
Developing "Safe" AI Hardware

Conference - May 07, 2024 Shaumik Ganguly

In this session, you will learn the challenges that AI/ML technologies pose for the safety of autonomous driving vehicles, and how can standards help to get AI/ML technology safely into the car.
Coverage Closure Acceleration Using Collaborative Verification IQ Tool

Conference - May 07, 2024 Suma Ramanand - Nokia

In this session, you will learn that ever-increasing design complexity and shortening design-to-market has demanded faster and more accurate functional verification. Industry surveys indicate that design engineers spend about half of their time on functional verification, and the situation has not improved over the years. Of all the verification tasks, increasing efforts have been spent on coverage analysis which is a major criterion for design sign-off.
Optimizing Connectivity Verification Workflow with Python and Tcl Scripting

Conference - May 07, 2024 Ariel Ansbacher

In this session, you will learn that Veriest’s client SiPearl was using a Defacto SoC-Compiler for generating connections between signals in their design. They were tasked to conduct connectivity checks on it, where the only available information about the signals connections was the Tcl file used to feed the SoC-Compiler. Veriest will walk through the steps taken to solve the challenge.
Extraction of Physical Macro from Top VC File

Conference - May 07, 2024 Nirav Patel

A normal SoC has many physical partitions compiled in different libraries involving multiple IPs with a very large file list referred to internally (at Arm) as the VC file list. In this session, you will learn how the automation from Siemens around Questa Visualizer is used to create the VC list for all physical partitions.
Enhanced Randomization and Functional Coverage: Make Better VHDL Testbenches

Conference - May 07, 2024 Espen Tallaksen

In this session, you will learn that UVVM’s advanced and optimized randomization and functional coverage was developed in cooperation with ESA (European Space Agency). In UVVM, understanding and readability of these features have been taken to a new level and UVVM also introduces functionality not previously available for VHDL testbenches. The user threshold is far lower than SystemVerilog and makes it easy for VHDL designers to use this advanced functionality.
Combined Formal and Functional Verification Approach for Digitally Controlled Analog Frontend

Conference - May 07, 2024 Mihajlo Katona

In this session, we present a fusion of formal and dynamic verification methods we applied in a mixed signal IC project. The challenge for DV verification team was to select the most suitable verification method. The idea here was to save time on top-level integration where only integration of one sub-system is required. With this experience, we learned that formal verification can significantly speed-up design bug discoveries and improve functional definitions in the system specification.
New AI Horizons in Static & Formal Verification

Resource (Recording) - Apr 24, 2024 Dan Yu
New AI Horizons in Static & Formal Verification

Resource (Slides (.PDF)) - Apr 24, 2024 Dan Yu
Optimizing FPGA Equivalence Checking for A&D Designs

Resource (Slides (.PDF)) - Apr 24, 2024 Kevin Urish
Driving Efficient Execution with Continuous Integration

Resource (Slides (.PDF)) - Apr 24, 2024 Kevin Campbell
Enverite PV-Bit: Bitstream Verification for FPGA Design Assurance

Resource (Slides (.PDF)) - Apr 24, 2024 Dr. Jonathan Graf
osmosis Aerospace and Defense 2024

Conference - Apr 24, 2024 John Hallman

osmosis Aerospace and Defense (A&D) is about sharing the success in using formal techniques to address the demanding verification requirements and challenges of Trust and Assurance verification, Safety Critical Designs, and DO-254 compliant and other high-consequence systems.
Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim

Resource (Slides (.PDF)) - Apr 16, 2024 Rich Edelman

In this webinar we will highlight the key innovations in QuestaSim that enable full debug visibility with significant reduction in simulation performance overhead and waveform database size.
Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim

Webinar - Apr 16, 2024 Rich Edelman

Root causing RTL design or simulation testbench bugs can be tedious process, especially if just relying on traditional waveform viewing and debug. Also, it can be costly if more sophisticated debug ties up precious simulation resources during the debug process.
Techniques to Identify Reset Metastability Due to Soft Resets

Resource (Paper (.PDF)) - Apr 15, 2024 Reetika

In this paper, we present a systematic methodology, as a part of static analysis, to intelligently identify critical reset domain bugs associated with soft resets. A soft reset is a mechanism that initiates a controlled reset within the system without fully powering it off.
Techniques to Identify Reset Metastability Due to Soft Resets

Paper - Apr 15, 2024 Reetika

Modern SoCs are equipped with complex reset architectures to meet the requirements of high-speed interfaces with increased functionality. In this paper, we present a systematic methodology, as a part of static analysis, to intelligently identify critical reset-domain bugs associated with soft resets. A soft reset is a mechanism that initiates a controlled reset within the system without fully powering it off.
Lost in Code: Using Visualizer to Understand Someone’s UVM Testbench

Conference - Apr 04, 2024 Salil Pandit

It's always challenging for Design/Verification engineers to take over the ongoing complex testbench work from another engineer who is no longer working on the given project. In this session, we walk through five (5) concrete steps you can take to fully understand a “new to you” UVM testbench.
Lost in Code: Using Visualizer to Understand Someone’s UVM Testbench

Resource (Slides (.PDF)) - Apr 04, 2024 Salil Pandit

It's always challenging for Design/Verification engineers to take over the ongoing complex testbench work from another engineer who is no longer working on the given project. In this session, we walk through five (5) concrete steps you can take to fully understand a “new to you” UVM testbench.
Why and How We Migrated from In-house Regression Management and Coverage Flow to Verification IQ

Conference - Apr 04, 2024 Avinash Agrawal

In this session, we share how we worked with a customer to migrate from a sophisticated array of home-grown spreadsheets and scripts to process coverage analysis automation with Questa Verification IQ.
Why and How We Migrated from In-house Regression Management and Coverage flow to Verification IQ

Resource (Slides (.PDF)) - Apr 04, 2024 Avinash Agrawal

In this session, we will go over how Verification IQ’s Coverage Analyzer and Regression Navigator helped us close coverage and regressions quicker and get more efficient usage out of our verification coverage cycles.
How and Why We Adopted Questa Core in the Development of Quantum Computers

Conference - Apr 04, 2024 Jan Marjanovic

This session starts with the introduction of our quantum computers and their control system, presents the challenges of verifying designs of decent complexity with constantly-changing requirements, discusses advantages and disadvantages of using Vivado Simulator and Questa Core for verification, and touches on the challenges of integrating Vivado and Questa Core.
How and Why We Adopted Questa Core in the Development of Quantum Computers

Resource (Slides (.PDF)) - Apr 04, 2024 Jan Marjanovic

This session starts with the introduction of our quantum computers and their control system, presents the challenges of verifying designs of decent complexity with constantly-changing requirements, discusses advantages and disadvantages of using Vivado Simulator and Questa Core for verification, and touches on the challenges of integrating Vivado and Questa Core.