Upcoming Webinar

Simulating AMD’s next-gen Versal Adaptive SoC devices using QuestaSim

Wednesday, July 24th - 8:00 AM US/Pacific

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1672 Results

  • Simulating AMD’s Next-gen Versal Adaptive SoC Devices using QuestaSim

    In this session, you will be provided with an in-depth guide on running simulation flows for a Versal Adaptive SoC. Additionally, we'll delve into QEMU, the open-source system emulator, and its co-simulation interface with Questa. Demonstrating how to conduct a system simulation of a Versal example design will be a focal point, showcasing Questa’s support for system simulation of Versal designs based on the Vitis™ hardware emulation flow.

  • Beyond Speed: Unlocking Productivity in Simulation and Debug

    Gone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity in today's fast-paced development environment. In this session we explore how Siemens EDA prioritizes productivity and performance, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.

  • Questa Verification IQ: Boost Verification Predictability and Efficiency with Collaboration, Traceability, and AI/ML Analytics

    This session will cover Questa Verification IQ (VIQ), the next-generation, data-driven verification solution from Siemens EDA that transforms the verification process using collaboration, traceability, and analytics. VIQ enables greater collaboration among teams and utilizes machine learning and AI to boost verification productivity and efficiency.

  • Functional Monitoring: From Lab to In-Life

    In this session, you will learn how Tessent Embedded Analytics helps deal with the systemic complexity of large SoCs, providing intimate visibility of the real-world behavior of entire systems.

  • The New Leader in Verification IP: Questa + Avery Solutions

    Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.

  • The New Leader in Verification IP: Questa + Avery Solutions

    Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.

  • Improve Productivity and Deliver Hardware Assurance: Stimulus-free Verification

    Learn how Siemens' and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.

  • Learn about the Security-critical CMA/SPDM, DOE, IDE, and TDISP elements of the PCIe protocol at the 2024 PCI SIG DevCon

    The Peripheral Component Interconnect Express (PCIe®) protocol is incredibly feature rich; so much so that even experienced engineers can struggle to keep up with the latest enhancements and capabilities. Hence, the “PCI SIG” standards organization holds an annual conference for D&V engineers to learn directly from the industry’s PCIe experts via technical training sessions; sharing best practices to ultimately improve product roll-out and interoperability.

  • Mark your calendar for the 2024 DAC-Chips to Systems Conference

    Get ready and mark your calendars for DAC 61 – the Chips to Systems Conference you won’t want to miss! As the ultimate event for all things chips to systems, DAC offers top-notch training, education, exhibits, and unbeatable networking opportunities for designers, researchers, tool developers, and vendors alike. This year, we’re thrilled to announce that Siemens is DAC’s first-ever Diamond Sponsor, shining bright at booth #2521.

  • Questa RDC Assist – Improving Designer Productivity and Enabling Faster RDC Verification Closure with Machine Learning

    In this session, you will learn how RDC Assist helps users expedite their RDC Analysis and will discuss use models and best practices to utilize RDC Assist, and walk through a demo showing its power.

  • Questa RDC Assist – Improving Designer Productivity and Enabling Faster RDC Verification Closure with Machine Learning

    In this session, you will learn how RDC Assist helps users expedite their RDC Analysis and will discuss use models and best practices to utilize RDC Assist, and walk through a demo showing its power.

  • Navigating Reset Domain Crossings to Safety in Complex SoCs

    As the complexity of system-on-chip (SoC) designs escalates, driven by the demand for more integrated functionalities and higher performance, electronic components such as processors, power management blocks, and DSP cores are proliferating. This surge necessitates a shift towards intricate power and performance management strategies, often incorporating several asynchronous and soft resets.

  • Developing “Safe” AI Hardware

    In this session you will learn the challenges that AI/ML technologies pose for the safety of autonomous driving vehicles, and how can standards help to get AI/ML technology safely into the car.

  • Coverage Closure Acceleration Using Collaborative Verification IQ Tool

    In this session you will learn that ever-increasing design complexity and shortening design-to-market has demanded faster and more accurate functional verification.

  • Optimizing Connectivity Verification Workflow with Python and Tcl Scripting

    In this session you will learn that Veriest’s client SiPearl was using a Defacto SoC-Compiler for generating connections between signals in their design. They were tasked to conduct connectivity checks on it, where the only available information about the signals connections was the Tcl file used to feed the SoC-Compiler. Veriest will walk through the steps taken to solve the challenge.

  • Extraction of VC File for Physical Macro From Top VC File

    A normal SoC has many physical partitions compiled in different libraries involving multiple IPs with a very large file list referred to internally (at Arm) as the VC file list. In this session you will learn how the automation from Siemens around Questa Visualizer is used to create the VC list for all physical partitions.

  • Improving Simulation Performance Utilizing the Visualizer Profiler

    In this session you will learn how Visualizer Profiler was used to identify areas for improvement within Arm VIP components and how these issues were addressed, reducing simulation time that were achieved due to these optimizations.

  • Enhanced Randomization and Functional Coverage – Make Better VHDL Testbenches

    In this session you will learn that UVVM’s advanced and optimized randomization and functional coverage was developed in cooperation with ESA (European Space Agency).

  • Combined Formal and Functional Verification Approach for Digitally Controlled Analog Frontend

    In this session we are presenting a fusion of formal and dynamic verification methods we applied in a mixed signal IC project. The challenge for DV verification team was to select the most suitable verification method.

  • Osmosis Aerospace and Defense 2024

    Osmosis Aerospace and Defense (A&D) is about sharing the success in using formal techniques to address the demanding verification requirements and challenges of Trust and Assurance verification, Safety Critical Designs, and DO-254 compliant and other high-consequence systems.

  • Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim

    In this webinar we will highlight the key innovations in QuestaSim that enable full debug visibility with significant reduction in simulation performance overhead and waveform database size.

  • Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim

    Root causing RTL design or simulation testbench bugs can be tedious process, especially if just relying on traditional waveform viewing and debug. Also, it can be costly if more sophisticated debug ties up precious simulation resources during the debug process.

  • Lost in Code: Using Visualizer to Understand Someone’s UVM Testbench

    It's always challenging for Design-Verification engineers to take over the ongoing complex testbench work from another engineer who is no longer working on the given project. In this presentation, we walk through 5 concrete steps you can take to fully understand a “new to you” UVM testbench.

  • Lost in Code: Using Visualizer to Understand Someone’s UVM Testbench

    It's always challenging for Design-Verification engineers to take over the ongoing complex testbench work from another engineer who is no longer working on the given project. In this presentation, we walk through 5 concrete steps you can take to fully understand a “new to you” UVM testbench.

  • Why and How We Migrated from In-house Regression Management and Coverage flow to Verification IQ

    In this session we share how we worked with a customer to migrate from a sophisticated array of home-grown spreadsheets and scripts to process coverage analysis automation with Questa Verification IQ.