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Simplify Scripting Environment using Qrun Capabilities in QuestaSim
Webinar - Nov 13, 2024 by Tom Kiley
In this session, we’ll walk you through the qrun flow and talk about the various scenarios where it can help over the traditional flow. We will also dive into our new QIS flows that help balance performance and design access. Our Visualizer debug environment is now part of every QuestaSim! We will walk through how to launch Visualizer from qrun and show you the benefits of running Visualizer. We’ll also be showcasing a new feature as part of the Visualizer presentation.
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Verification Academy Live: Austin
Seminar - Nov 06, 2024 by Joe Hupcey
This seminar will update you on technologies and techniques you can adopt to increase your verification productivity today. Wednesday, November 6th | 9:30 AM - 5:00 PM | Austin, Texas
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Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications
Webinar - Oct 30, 2024 by Kamlesh Mulchandani
In this session, you will learn how Siemens’s scalable and customizable Avery HBM Verification IP helps companies like Rambus verify their industry-leading HBM4 Controller IP through rigorous testing to ensure reliability and performance.
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Securing the Future: A Deep Dive into Cryptography and Data Protection
Resource (Verification Horizons Blog) - Oct 11, 2024 by Suprio Biswas - Siemens EDA
Cryptography and data protection mechanisms form the cornerstone of this defence, ensuring that communication between devices remains confidential, authentic, and unhampered. Two key players in this domain are Component Measurement and Authentication (CMA) and the Security Protocol and Data Model (SPDM). Together, they provide a robust framework for securing communications, particularly in PCIe (Peripheral Component Interconnect Express) systems.
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Celebrating the Approval of Portable Test and Stimulus Standard (PSS) 3.0
Resource (Verification Horizons Blog) - Oct 09, 2024 by Dennis Brophy - Siemens EDA
Accellera Systems Initiative has recently announced the approval of the Portable Test and Stimulus Standard (PSS) 3.0 , marking a significant milestone in verification of electronic systems. My colleague, Tom Fitzpatrick, wrote a nice blog a few weeks before the announcement highlighting his video presentation on how PSS and Verification IP fit together like a hand in a glove at DAC.
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Increasing Fault Coverage with Siemens Functional Fault Grading Solutions
Resource (Fact Sheet) - Oct 08, 2024 by Ann Keffer
In this session, you will learn five important aspects of why you should implement functional fault grading.
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Accelerating Verification Closure with Siemens DFT Tailored Verification Solutions
Resource (Slides) - Oct 08, 2024 by Jacob Wiltgen
In this session, you will be introduced to the Questa DFT Verification Platform, a comprehensive, high-productivity DFT verification solution.
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Embracing a New Era in DFT: Addressing High Defect Coverage, Silent Data Errors, and Emerging Challenges
Resource (Slides) - Oct 08, 2024 by Lee Harrison
In this session, you will learn Tessent's approach to Silicon Lifecycle Management (SLM).
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Understanding and Navigating the New Challenges in Design-for-Test
Resource (Slides) - Oct 08, 2024 by Lee Harrison
In this session, you will learn that Tessent deploys techniques to reduce simulation effort where possible.
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The Osmosis Formal Verification Conference Celebrates its 5th anniversary!
Resource (Verification Horizons Blog) - Sep 26, 2024 by Joe Hupcey
Calling all formal verification enthusiasts: We are excited to invite you to osmosis 2024, marking the 5th anniversary of this premier formal verification event where experts in come together to share cutting-edge solutions and success stories. Following DVCon Europe on October 17th in the same Munich venue — with more speakers than ever before — this year’s osmosis promises to be a day of deep learning, collaboration, and networking with professionals dedicated to advancing formal methods.
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Universal Verification Methodology (UVM): VIP Challenges & Effective Deployment Guide
Resource (Slides) - Sep 18, 2024 by Jeffrey Jacobson - L3Harris
This session will give a brief overview of the UVM, introduce Verification Intellectual Property (VIP) and cover benefits for using industry standard VIPs. We will delve into challenges faced with deploying VIPs, including protocol complexities, training, and critically tailoring/tuning the VIP for your target interface for FPGAs or ASICs. We present step-by-step flowchart to plan, budget, train, ramp-up, pre-validate, adopt, and successfully deploy VIPs on projects.
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Questa Verification IQ: Boost Verification Predictability and Efficiency with Collaboration, Traceability, and AI/ML Analytics
Resource (Slides) - Sep 18, 2024 by Austin Mam
This session will cover Verification IQ (VIQ), the next-generation, data-driven verification solution from Siemens EDA that transforms the verification process using collaboration, traceability, and analytics. VIQ enables greater collaboration among teams and utilizes machine learning and AI to boost verification productivity and efficiency.
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Challenges of Multiple FPGA Tool Flow Verification
Resource (Slides) - Sep 18, 2024 by Paul Bobko - Westinghouse Electric
This session will examine the challenges of utilizing common RTL for different FPGA targets. Each FPGA target requires a different tool flow, therefore verification of each tool flow is necessary in determining functional accuracy. Traditionally, functional verification has been sufficient to guard against tool flow issues. Functional safety requirements necessitate a more robust verification process. Equivalency checking ensures that a tool flow defect is not realized in the final product.
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Questa Equivalent FPGA: Assuring FPGA Integrity
Resource (Slides) - Sep 18, 2024 by Martin Rowe
Questa Equivalent RTL allows FPGA designers to utilize equivalency checking principles on FPGAs with access to vendor libraries allowing proper analysis of low-level primitives e.g. native RAM and DSP elements. The tool was recently explored at Northrop Grumman to verify the functional equivalence of firmware targeted to FPGAs from different vendors. We found that Questa Equivalent RTL’s ability to support FPGA device primitives to be incredibly useful and unique among similar industry tools.
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Transforming AI with HBM: Siemens’ Avery VIP powers Rambus’ Industry-First HBM4 Memory Controller
Resource (Slides) - Sep 18, 2024 by Vivek Kaliki - Siemens EDA
The semiconductor industry is entering a new era, driven by advancements in memory technology and the growing influence of artificial intelligence (AI). As AI continues to evolve, hardware infrastructure is facing increasing challenges, with memory performance emerging as a critical bottleneck.
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Exploring Essential Concepts in Formal Verification
Resource (Verification Horizons Blog) - Sep 18, 2024 by Nicolae Tusinschi
A witness is a sequence of inputs that demonstrates how an assertion is satisfied, showing that the design behaves as expected. A counterexample, on the other hand, is a sequence of inputs that violates an assertion, indicating a potential bug or design flaw. Both can be used to generate simulation tests that help engineers debug and verify the design.
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MARLUG - 2024
Seminar - Sep 18, 2024 by Austin Mam
User2User Mid-Atlantic is your opportunity to learn, grow and connect with fellow technical experts who design leading-edge products using Siemens EDA tools.
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Assertions and Benefits of Abstractions in Formal Verification
Resource (Verification Horizons Blog) - Sep 11, 2024 by Nicolae Tusinschi
Assertions are typically specified using languages like SystemVerilog Assertions (SVA) or Property Specification Language (PSL). These languages provide constructs for expressing complex design behaviors, making it possible to verify a wide range of conditions and scenarios.
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Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs
Webinar - Sep 11, 2024 by Nicolae Tusinschi
In this session, you will learn how Questa Formal Verification IP (VIP) for the AMBA protocol ensures that designs incorporating AMBA adhere strictly to the protocol; all without the need for simulation. The solution integrates comprehensive protocol knowledge, providing user-friendly interfaces, significantly reducing verification environment setup time. Optimized for top-tier performance and scalability, Questa Formal VIP AMBA achieves high-efficiency with accurate protocol compliance.
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Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs
Resource (Slides) - Sep 11, 2024 by Nicolae Tusinschi
Questa Formal VIP AMBA is the ideal tool for achieving high-efficiency and accurate protocol compliance. Don't miss this opportunity to learn how to streamline your verification process and enhance your design workflows.
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Understanding Formal Verification
Resource (Verification Horizons Blog) - Sep 05, 2024 by Nicolae Tusinschi
Formal verification is a method to ensure that a hardware design behaves as intended by using mathematical analysis to check its correctness relative to its specifications. Unlike traditional verification methods, which rely on testing and simulation, formal verification mathematically proves that a design will always function correctly under all possible scenarios.
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Jump-Start Your UVM Journey with UVM Framework (UVMF)
Resource (Verification Horizons Blog) - Sep 04, 2024 by Dennis Brophy - Siemens EDA
Bob Oden shares insights on how the Universal Verification Methodology Framework (UVMF) is revolutionizing the verification landscape. UVMF is an advanced toolset that extends the capabilities of UVM, providing a robust and structured approach to verification.
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The Future of Multi-Die System Verification with UCIe
Resource (Slides) - Aug 21, 2024 by Justin Bunnell
Universal Chiplet Interconnect express (UCIe) is an open chiplet interconnect standard that enables efficient connectivity and interoperability between multiple dies on the same package. This solution offers numerous benefits including low power consumption, high bandwidth, multiple protocol support, and interoperability between chiplets of varying performance characteristics.
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The Future of Multi-Die System Verification with UCIe
Webinar - Aug 21, 2024 by Justin Bunnell
In this session, you will be introduced to the UCIe protocol with a focus on the latest evolutions of the specification, followed by a deep dive into the key features of Siemens Avery UCIe Verification IP that enable efficient verification of multi-die systems. These include dynamic block-level and System-in-Package (SiP) level testbench creation, intelligent traffic generation, error injection, advanced debug features, and comprehensive performance monitoring.
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Advanced Analytics for Accelerating RDC Verification Closure
Resource (Verification Horizons Blog) - Aug 13, 2024 by Reetika - Siemens EDA
Complex reset mechanisms are embedded in advanced SoCs to meet low-power and high-performance requirements. Multiple reset domains in a design can cause reset domain crossing (RDC) issues when data from one asynchronous source reset domain propagates to either a different asynchronous, synchronous, or no-reset destination domain.