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Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim

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1599 Results

  • Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim

    Root causing RTL design or simulation testbench bugs can be tedious process, especially if just relying on traditional waveform viewing and debug. Also, it can be costly if more sophisticated debug ties up precious simulation resources during the debug process.

  • Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification

    Gate-level simulations (GLS) are a crucial step in the verification of an ASIC/FPGA. GLS is used for verifying power-up, reset operation, timing, multi-cycle paths, and power estimation. However, GLS can be a bottleneck in the project cycle due to its complexity.

  • Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification

    This session will describe a reliable formal-based method to manage Xs in GLS. It centers on the use of Siemens Avery SimXACT solution alongside your preferred simulator.

  • In Memoriam: Chris Spear

    Our friend and colleague Chris Spear passed away suddenly. He was a long-time veteran of our industry and was known and respected by many.

  • New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

    In this session, you will learn new RDC, methodology, and automation techniques including; how to hierarchically characterize and structure reset (and clock) domain models for rapid analysis and re-use of IP-level RDC information as the design grows, waiver management flows, creating custom synchronizers and considerations for low power designs with UPF.

  • New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

    In this session, you will learn new RDC, methodology, and automation techniques including; how to hierarchically characterize and structure reset (and clock) domain models for rapid analysis and re-use of IP-level RDC information as the design grows, waiver management flows, creating custom synchronizers and considerations for low power designs with UPF.

  • Get your free copy of the IEEE 1800-2023 SystemVerilog LRM

    At last year’s Design & Verification Conference (DVCon), I presented a few changes to the upcoming revision to the SystemVerilog standard. After a year of two rounds of balloting, the final revision is being published. The great news is many of these “new” features are already available in existing tools, or being worked on.

  • Enhancing PCIe Verification: How to Step Off the Map

    This article intends to propose a range of strategies that an RC might use to ‘generate’ addresses that fall outside the standard scope, along with a detailed examination of the subtle complexities involved. Initially, we will explore two relatively simple methods to accomplish this. Following that, we will analyze the limitations inherent in these methods.

  • Tool Assisted Debug in Visualizer

    Verification is one of the primary challenges in current times when designs are huge, and corresponding testbenches are equally large. Both the design and testbench work together to fulfill the desired expectations of the designer. Everything goes well until the simulation does not work as expected. This is where Visualizer, the debug platform, plays a crucial role in figuring out where the problem lies. Visualizer requires multiple databases to provide the debug features.

  • Formal Verification: An Introduction and Exploration of Challenges

    Nowadays, the formal verification is getting more popular compared to the conventional simulation-based verification. The main idea behind the formal verification is to mathematically prove or disprove the correctness of a design with respect to the specification or requirement and ensure that the design behaves as intended under all possible scenarios. To achieve this, the formal verification tools are using Satisfiability Modulo Theories (SMT) solver engines.

  • Maximize Returns on Your Hardware Emulation Investment with the Veloce Enterprise (ES) App

    Hardware-Assisted verification (HAV) with emulation is widely regarded as crucial for successfully designing, verifying, and deploying large ASICs and even FPGAs. An emulator is a major capital investment, and customers are highly motivated to get the maximum benefit from their expenditure.

  • A True Native 64-bit Vedic Multiplier Boosts Performance for Processors, Multi-Cores and DSP

    This article introduces a revolutionary 64-bit native Vedic multiplier design, inspired by the Urdhva Tiryagbhyam sutra-based algorithm by Scientist Bharati Krishna Tirtha. The architecture offers superior power, timing, and area optimization, showcasing its potential for Processors, multi-cores, and DSPs computation needs. The differentiator between the current implementation and to past is the vastly enhanced native implementation of the algorithm.

  • A True Native 64-bit Vedic Multiplier Boosts Performance for Processors, Multi-Cores and DSP

    This article introduces a revolutionary 64-bit native Vedic multiplier design, inspired by the Urdhva Tiryagbhyam sutra-based algorithm by Scientist Bharati Krishna Tirtha. The architecture offers superior power, timing, and area optimization, showcasing its potential for Processors, multi-cores, and DSPs computation needs. The differentiator between the current implementation and to past is the vastly enhanced native implementation of the algorithm.

  • DVCon 2024 – Verify Real Number Models

    Do you like to solve puzzles? I do, and I think every engineer does. Since we are solving puzzles every day, there is always a masterpiece that could complete your puzzle. The masterpiece could be any internal piece of puzzle that could complete your final image. Verifying the complete image of your puzzle by putting internal pieces one after another, could help make you reach the final picture.

  • UVM Objections at DVCON US 2024 – and Grape Jelly

    It’s been a while – busy. Too busy to be in the garden. But last fall we realized the grape plants in the yard produced a ton of grapes – at least it looked like a ton to us. What to do? Instead of letting the birds eat all the grapes, we decided to make jelly. I’ve made jelly before – it’s not hard, but it can (and did) go wrong. (See – already like the UVM)

  • Comprehensive CXL 3.0 Verification for High-Bandwidth and Low-Latency Connectivity

    In this session, you will learn considerations for exhaustive verification of the CXL interconnect and how the Siemens Avery CXL Validation Suite enables hardware and software development teams to start system integration and validation extremely early.

  • Join us at DVCon for a panel on Generative AI

    Step into the enhanced Verification Academy 2.0! After a year of meticulous development, we are thrilled to unveil its array of exciting new capabilities. For those unfamiliar with the Verification Academy, it stands as the foremost online resource for advanced functional verification learning. We are committed to assisting you in mastering advanced functional verification skills, unlocking the numerous benefits it brings to the table.

  • Functional Verification workflow for Trusted and Assured Microelectronics

    In this session, we will introduce apps that provide advanced automated functional checking, secure data path verification, trustworthiness assessment, and equivalence checking for extending the foundation of functional verification to attack the complex IC integrity challenges of today.

  • Functional Verification workflow for Trusted and Assured Microelectronics

    In a world of increasing trust and assurance challenges for microelectronic devices, emerging industry standards and defense policy demand early and advanced functional verification methods before ICs may be deployed in critical end products and systems. Questa technologies, built upon a foundation of world-class simulation and formal engines, provide the results desired for raising and meeting higher levels of trust and assurance for microelectronic designs.

  • Welcome to the Enhanced Verification Academy 2.0 Forums!

    The Verification Academy is the industry’s leading resource to help you learn how to develop the skills and techniques to advance your organization’s functional verification process. It also provides forums where you can ask questions and get answers from industry peers on these verification topics. We’ve optimized the site for better viewing on a wide variety of devices, including mobile phones and tablets.

  • Comprehensive PCIe Verification Solution for Bleeding Edge and Mission Critical SoC & IP Designs

    Applications such as Data Centers, High-Performance computing (HPC), artificial intelligence/machine learning (AI/ML), cloud computing, military, and aerospace, automotive, etc. are all extremely Bandwidth-hungry. To cater to such high demands of high speeds and bandwidth requires a breakthrough that HPC SoCs are constantly facing.

  • Comprehensive PCIe Verification Solution for Bleeding Edge and Mission Critical SoC & IP Designs

    In this session, you will learn design considerations for PCIe 5.0 and 6.0 design IP and how you can stay ahead in the market in verifying the most advanced and critical features of PCIe 6.0 and 5.0 for your design IPs.

  • Welcome to Verification Academy 2.0!

    Step into the enhanced Verification Academy 2.0! After a year of meticulous development, we are thrilled to unveil its array of exciting new capabilities. For those unfamiliar with the Verification Academy, it stands as the foremost online resource for advanced functional verification learning. We are committed to assisting you in mastering advanced functional verification skills, unlocking the numerous benefits it brings to the table.

  • UVM Framework Release 2023.4

    Generator Updates: Generated qvip.compile files do not include hvl module generated by QVIP configurator when only QVIP protocols selected. BCR Updates: New step added for command line execution. Any number of these steps can be added to accommodate external commands as needed. See overlay_example.flow for details.

  • IEEE Honors Siemens Employees for Dedication to Standards Development

    Annually, the IEEE Standards Association (IEEE SA) recognizes outstanding participation across a variety of technical areas of standards development, leadership, and distinguished service. The IEEE SA awards ceremony was held in early December and among the awardees are two from Siemens EDA. You may recognize the names as they are two of our Verification Horizons bloggers as well.