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1771 Results

VeriCHERI: Exhaustive Formal Security Verification of CHERI at the RTL

Resource (Recording) - Oct 17, 2024 by Johannes Muller - Rheinland-Pfälzische
VeriCHERI: Exhaustive Formal Security Verification of CHERI at the RTL

Resource (Slides) - Oct 17, 2024 by Johannes Muller - Rheinland-Pfälzische
Formal Methodology as a Powerful Approach for RISC-V Customization Verification

Resource (Recording) - Oct 17, 2024 by Adrian Javor - Codasip
Formal Methodology as a Powerful Approach for RISC-V Customization Verification

Resource (Slides) - Oct 17, 2024 by Adrian Javor - Codasip
Empowering Issue Hunting Mode Verification on RISC-V Architectures

Resource (Recording) - Oct 17, 2024 by Teo Bernier - Thales Group
Empowering Issue Hunting Mode Verification on RISC-V Architectures

Resource (Slides) - Oct 17, 2024 by Teo Bernier - Thales Group
Taming Formal with Intelligent Automation?

Resource (Recording) - Oct 17, 2024 by Tobias Ludwig - Lubis EDA
Taming Formal with Intelligent Automation?

Resource (Slides) - Oct 17, 2024 by Tobias Ludwig - Lubis EDA
Achieving Efficient Verification Combining Simulation and Formal

Resource (Slides) - Oct 17, 2024 by Ilia Barkov - Semidynamics
Achieving Efficient Verification Combining Simulation and Formal

Resource (Recording) - Oct 17, 2024 by Ilia Barkov - Semidynamics
osmosis 2024

Conference - Oct 17, 2024 by Nicolae Tusinschi

The annual osmosis event is a dynamic platform for exchanging successes achieved through applying formal techniques to overcome verification challenges. It offers a unique opportunity to connect and engage with our accomplished research and development (R&D) experts and participants. The conversations that follow may help you and others improve formal-based verification solutions.
Securing the Future: A Deep Dive into Cryptography and Data Protection

Resource (Verification Horizons Blog) - Oct 11, 2024 by Suprio Biswas - Siemens EDA

Cryptography and data protection mechanisms form the cornerstone of this defence, ensuring that communication between devices remains confidential, authentic, and unhampered. Two key players in this domain are Component Measurement and Authentication (CMA) and the Security Protocol and Data Model (SPDM). Together, they provide a robust framework for securing communications, particularly in PCIe (Peripheral Component Interconnect Express) systems.
Celebrating the Approval of Portable Test and Stimulus Standard (PSS) 3.0

Resource (Verification Horizons Blog) - Oct 09, 2024 by Dennis Brophy - Siemens EDA

Accellera Systems Initiative has recently announced the approval of the Portable Test and Stimulus Standard (PSS) 3.0 , marking a significant milestone in verification of electronic systems. My colleague, Tom Fitzpatrick, wrote a nice blog a few weeks before the announcement highlighting his video presentation on how PSS and Verification IP fit together like a hand in a glove at DAC.
Increasing Fault Coverage with Siemens Functional Fault Grading Solutions

Resource (Fact Sheet) - Oct 08, 2024 by Ann Keffer

In this session, you will learn five important aspects of why you should implement functional fault grading.
Accelerating Verification Closure with Siemens DFT Tailored Verification Solutions

Resource (Slides) - Oct 08, 2024 by Jacob Wiltgen

In this session, you will be introduced to the Questa DFT Verification Platform, a comprehensive, high-productivity DFT verification solution.
Embracing a New Era in DFT: Addressing High Defect Coverage, Silent Data Errors, and Emerging Challenges

Resource (Slides) - Oct 08, 2024 by Lee Harrison

In this session, you will learn Tessent's approach to Silicon Lifecycle Management (SLM).
Understanding and Navigating the New Challenges in Design-for-Test

Resource (Slides) - Oct 08, 2024 by Lee Harrison

In this session, you will learn that Tessent deploys techniques to reduce simulation effort where possible.
The osmosis Formal Verification Conference Celebrates its 5th anniversary!

Resource (Verification Horizons Blog) - Sep 26, 2024 by Joe Hupcey

Calling all formal verification enthusiasts: We are excited to invite you to osmosis 2024, marking the 5th anniversary of this premier formal verification event where experts in come together to share cutting-edge solutions and success stories. Following DVCon Europe on October 17th in the same Munich venue — with more speakers than ever before — this year’s osmosis promises to be a day of deep learning, collaboration, and networking with professionals dedicated to advancing formal methods.
Universal Verification Methodology (UVM): VIP Challenges & Effective Deployment Guide

Resource (Slides) - Sep 18, 2024 by Jeffrey Jacobson - L3Harris

This session will give a brief overview of the UVM, introduce Verification Intellectual Property (VIP) and cover benefits for using industry standard VIPs. We will delve into challenges faced with deploying VIPs, including protocol complexities, training, and critically tailoring/tuning the VIP for your target interface for FPGAs or ASICs. We present step-by-step flowchart to plan, budget, train, ramp-up, pre-validate, adopt, and successfully deploy VIPs on projects.
Questa Verification IQ: Boost Verification Predictability and Efficiency with Collaboration, Traceability, and AI/ML Analytics

Resource (Slides) - Sep 18, 2024 by Austin Mam

This session will cover Verification IQ (VIQ), the next-generation, data-driven verification solution from Siemens EDA that transforms the verification process using collaboration, traceability, and analytics. VIQ enables greater collaboration among teams and utilizes machine learning and AI to boost verification productivity and efficiency.
Challenges of Multiple FPGA Tool Flow Verification

Resource (Slides) - Sep 18, 2024 by Paul Bobko - Westinghouse Electric

This session will examine the challenges of utilizing common RTL for different FPGA targets. Each FPGA target requires a different tool flow, therefore verification of each tool flow is necessary in determining functional accuracy. Traditionally, functional verification has been sufficient to guard against tool flow issues. Functional safety requirements necessitate a more robust verification process. Equivalency checking ensures that a tool flow defect is not realized in the final product.
Questa Equivalent FPGA: Assuring FPGA Integrity

Resource (Slides) - Sep 18, 2024 by Martin Rowe

Questa Equivalent RTL allows FPGA designers to utilize equivalency checking principles on FPGAs with access to vendor libraries allowing proper analysis of low-level primitives e.g. native RAM and DSP elements. The tool was recently explored at Northrop Grumman to verify the functional equivalence of firmware targeted to FPGAs from different vendors. We found that Questa Equivalent RTL’s ability to support FPGA device primitives to be incredibly useful and unique among similar industry tools.
Transforming AI with HBM: Siemens’ Avery VIP powers Rambus’ Industry-First HBM4 Memory Controller

Resource (Verification Horizons Blog) - Sep 18, 2024 by Vivek Kaliki - Siemens EDA

The semiconductor industry is entering a new era, driven by advancements in memory technology and the growing influence of artificial intelligence (AI). As AI continues to evolve, hardware infrastructure is facing increasing challenges, with memory performance emerging as a critical bottleneck.
Exploring Essential Concepts in Formal Verification

Resource (Verification Horizons Blog) - Sep 18, 2024 by Nicolae Tusinschi

A witness is a sequence of inputs that demonstrates how an assertion is satisfied, showing that the design behaves as expected. A counterexample, on the other hand, is a sequence of inputs that violates an assertion, indicating a potential bug or design flaw. Both can be used to generate simulation tests that help engineers debug and verify the design.
MARLUG - 2024

Seminar - Sep 18, 2024 by Austin Mam

User2User Mid-Atlantic is your opportunity to learn, grow and connect with fellow technical experts who design leading-edge products using Siemens EDA tools.

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

Upcoming FPU Webinar

Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Upcoming Formal Security Webinar

Wednesday, Feb 05th-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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Resource (Recording) - Oct 17, 2024 by Johannes Muller - Rheinland-Pfälzische

Resource (Slides) - Oct 17, 2024 by Johannes Muller - Rheinland-Pfälzische

Resource (Recording) - Oct 17, 2024 by Adrian Javor - Codasip

Resource (Slides) - Oct 17, 2024 by Adrian Javor - Codasip

Resource (Recording) - Oct 17, 2024 by Teo Bernier - Thales Group

Resource (Slides) - Oct 17, 2024 by Teo Bernier - Thales Group

Resource (Recording) - Oct 17, 2024 by Tobias Ludwig - Lubis EDA

Resource (Slides) - Oct 17, 2024 by Tobias Ludwig - Lubis EDA

Resource (Slides) - Oct 17, 2024 by Ilia Barkov - Semidynamics

Resource (Recording) - Oct 17, 2024 by Ilia Barkov - Semidynamics

Conference - Oct 17, 2024 by Nicolae Tusinschi

Resource (Verification Horizons Blog) - Oct 11, 2024 by Suprio Biswas - Siemens EDA

Resource (Verification Horizons Blog) - Oct 09, 2024 by Dennis Brophy - Siemens EDA

Resource (Fact Sheet) - Oct 08, 2024 by Ann Keffer

Resource (Slides) - Oct 08, 2024 by Jacob Wiltgen

Resource (Slides) - Oct 08, 2024 by Lee Harrison

Resource (Slides) - Oct 08, 2024 by Lee Harrison

Resource (Verification Horizons Blog) - Sep 26, 2024 by Joe Hupcey

Resource (Slides) - Sep 18, 2024 by Jeffrey Jacobson - L3Harris

Resource (Slides) - Sep 18, 2024 by Austin Mam

Resource (Slides) - Sep 18, 2024 by Paul Bobko - Westinghouse Electric

Resource (Slides) - Sep 18, 2024 by Martin Rowe

Resource (Verification Horizons Blog) - Sep 18, 2024 by Vivek Kaliki - Siemens EDA

Resource (Verification Horizons Blog) - Sep 18, 2024 by Nicolae Tusinschi

Seminar - Sep 18, 2024 by Austin Mam