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1629 Results

  • A True Native 64-bit Vedic Multiplier Boosts Performance for Processors, Multi-Cores and DSP

    This article introduces a revolutionary 64-bit native Vedic multiplier design, inspired by the Urdhva Tiryagbhyam sutra-based algorithm by Scientist Bharati Krishna Tirtha. The architecture offers superior power, timing, and area optimization, showcasing its potential for Processors, multi-cores, and DSPs computation needs. The differentiator between the current implementation and to past is the vastly enhanced native implementation of the algorithm.

  • A True Native 64-bit Vedic Multiplier Boosts Performance for Processors, Multi-Cores and DSP

    This article introduces a revolutionary 64-bit native Vedic multiplier design, inspired by the Urdhva Tiryagbhyam sutra-based algorithm by Scientist Bharati Krishna Tirtha. The architecture offers superior power, timing, and area optimization, showcasing its potential for Processors, multi-cores, and DSPs computation needs. The differentiator between the current implementation and to past is the vastly enhanced native implementation of the algorithm.

  • DVCon 2024 – Verify Real Number Models

    Do you like to solve puzzles? I do, and I think every engineer does. Since we are solving puzzles every day, there is always a masterpiece that could complete your puzzle. The masterpiece could be any internal piece of puzzle that could complete your final image. Verifying the complete image of your puzzle by putting internal pieces one after another, could help make you reach the final picture.

  • UVM Objections at DVCON US 2024 – and Grape Jelly

    It’s been a while – busy. Too busy to be in the garden. But last fall we realized the grape plants in the yard produced a ton of grapes – at least it looked like a ton to us. What to do? Instead of letting the birds eat all the grapes, we decided to make jelly. I’ve made jelly before – it’s not hard, but it can (and did) go wrong. (See – already like the UVM)

  • Comprehensive CXL 3.0 Verification for High-Bandwidth and Low-Latency Connectivity

    In this session, you will learn considerations for exhaustive verification of the CXL interconnect and how the Siemens Avery CXL Validation Suite enables hardware and software development teams to start system integration and validation extremely early.

  • Join us at DVCon for a panel on Generative AI

    Step into the enhanced Verification Academy 2.0! After a year of meticulous development, we are thrilled to unveil its array of exciting new capabilities. For those unfamiliar with the Verification Academy, it stands as the foremost online resource for advanced functional verification learning. We are committed to assisting you in mastering advanced functional verification skills, unlocking the numerous benefits it brings to the table.

  • Functional Verification workflow for Trusted and Assured Microelectronics

    In this session, we will introduce apps that provide advanced automated functional checking, secure data path verification, trustworthiness assessment, and equivalence checking for extending the foundation of functional verification to attack the complex IC integrity challenges of today.

  • Functional Verification workflow for Trusted and Assured Microelectronics

    In a world of increasing trust and assurance challenges for microelectronic devices, emerging industry standards and defense policy demand early and advanced functional verification methods before ICs may be deployed in critical end products and systems. Questa technologies, built upon a foundation of world-class simulation and formal engines, provide the results desired for raising and meeting higher levels of trust and assurance for microelectronic designs.

  • Welcome to the Enhanced Verification Academy 2.0 Forums!

    The Verification Academy is the industry’s leading resource to help you learn how to develop the skills and techniques to advance your organization’s functional verification process. It also provides forums where you can ask questions and get answers from industry peers on these verification topics. We’ve optimized the site for better viewing on a wide variety of devices, including mobile phones and tablets.

  • Comprehensive PCIe Verification Solution for Bleeding Edge and Mission Critical SoC & IP Designs

    Applications such as Data Centers, High-Performance computing (HPC), artificial intelligence/machine learning (AI/ML), cloud computing, military, and aerospace, automotive, etc. are all extremely Bandwidth-hungry. To cater to such high demands of high speeds and bandwidth requires a breakthrough that HPC SoCs are constantly facing.

  • Comprehensive PCIe Verification Solution for Bleeding Edge and Mission Critical SoC & IP Designs

    In this session, you will learn design considerations for PCIe 5.0 and 6.0 design IP and how you can stay ahead in the market in verifying the most advanced and critical features of PCIe 6.0 and 5.0 for your design IPs.

  • Welcome to Verification Academy 2.0!

    Step into the enhanced Verification Academy 2.0! After a year of meticulous development, we are thrilled to unveil its array of exciting new capabilities. For those unfamiliar with the Verification Academy, it stands as the foremost online resource for advanced functional verification learning. We are committed to assisting you in mastering advanced functional verification skills, unlocking the numerous benefits it brings to the table.

  • UVM Framework Release 2023.4

    Generator Updates: Generated qvip.compile files do not include hvl module generated by QVIP configurator when only QVIP protocols selected. BCR Updates: New step added for command line execution. Any number of these steps can be added to accommodate external commands as needed. See overlay_example.flow for details.

  • IEEE Honors Siemens Employees for Dedication to Standards Development

    Annually, the IEEE Standards Association (IEEE SA) recognizes outstanding participation across a variety of technical areas of standards development, leadership, and distinguished service. The IEEE SA awards ceremony was held in early December and among the awardees are two from Siemens EDA. You may recognize the names as they are two of our Verification Horizons bloggers as well.

  • UVM Connect 2.3.3 Kit

    The uvmc-2.3.3 release adds better support for the semantics of the TLM-2.0 base protocol and how it is used in the context of 4-phase transactions.

  • UVM Connect 2.3.3 Primer

    The UVMC library is provided as a separate, optional package to UVM. You do not need to import the package if your environments do not require cross-language TLM connections or access to the UVM Command API.

  • UVM Connect 2.3.3 HTML

    The UVM Connect library provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog models and components. It also provides a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++).

  • Multi-Die System Verification with Siemens’s UCIe VIP

    Conventional monolithic SoCs are becoming a bottleneck for power, performance, and area (PPA), creating limitations for Data-intensive applications like high-performance computing (HPC), machine learning (ML) and artificial intelligence (AI), and for hyperscale data centers.

  • Multi-Die System Verification with Siemens’s UCIe VIP

    In this session, we will introduce you to Siemens EDA's Verification Portfolio and then deep dive into UCIe Verification IP, discussing its key features such as dynamic block-level and SoC level testbench creation, traffic generation, error injection, debug features, and performance monitoring. Siemens Avery UCIe Verification IP is a leading solution in the market, runs on all major simulators and is a native SystemVerilog/UVM class-based Verification IP.

  • Hierarchical verification flow for FPGA design projects

  • Limits of verification: learnings from catastrophic system failures

  • Reducing formal verification runtime in SystemC utilizing modular interface

  • Dusica Glisic - Veriest

    Interview with Dusica Glisic of Veriest about the value of attending Osmosis.

  • Mihajlo Katona - Veriest

    Interview with Mihajlo Katona of Veriest about his presentation on combining sim and formal, formal for security, FPGA, and HLS verification, HLS and formal - and advice on starting out with formal.

  • How to sign-off cryptographic hash implementations with generated formal assertions