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Verification Technology Trends
Session - Feb 17, 2025 by Harry Foster
Take a closer look at the adoption of advanced verification technologies such as formal verification, simulation, emulation, FPGA prototyping, and their impact on verification workflows.
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Final Insights and Conclusions
Session - Feb 17, 2025 by Harry Foster
Summarizing key takeaways from the study, this video highlights the most significant trends, challenges, and opportunities shaping the future of ASIC and FPGA verification.
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Got Coverage?
Resource (Verification Horizons Blog) - Feb 14, 2025 by Rich Edelman
Welcome to 2025. What happened?! “Coverage” in August in Yosemite backpacking has a different meaning. In August? Snow? Lots of coverage. Got Coverage? But, nevermind – what about YOUR coverage!? You didn’t get enough coverage collected. But just maybe you have a bunch of 0’s and 1’s. You’re late with your coverage, but your old school 0’s and 1’s are going to save the day.
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DVCon 2025: A Must for Hardware Design and Verification Engineers
Resource (Verification Horizons Blog) - Feb 12, 2025 by Dave Rich
I’ve attended every DVCon US conference since its inception, over 30 years ago. I’ve also given keynotes at DVCon India. Now I’m the DVCon US vice program chair and am looking forward to being the program chair in 2026. I can honestly say this conference is an unparalleled opportunity for design and verification engineers. DVCon U.S. 2025 continues to uphold the DVCon reputation as the premiere event for our community, offering a unique venue to learn, network, and exchange ideas face-to-face.
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Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator
Resource (Slides Download) - Feb 12, 2025 by Mark Carey
In this webinar, we explore the powerful smart regression features of collaborative browser-based data-driven verification. You will then learn how to harness the full potential of Questa Verification IQ to boost efficiency and productivity in your verification efforts, take advantage of automating the detection of design differences and optimize regression time by maximizing compute resources.
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Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator
Webinar - Feb 12, 2025 by Mark Carey
In this webinar, we explore the powerful smart regression features of collaborative browser-based data-driven verification. You will then learn how to harness the full potential of Questa Verification IQ to boost efficiency and productivity in your verification efforts, take advantage of automating the detection of design differences and optimize regression time by maximizing compute resources.
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Siemens at DVCon 2025: Don’t Miss the Luncheon and More!
Resource (Verification Horizons Blog) - Feb 11, 2025 by Harry Foster
The latest trends in verification are in—and they’re more than just surprising. They’re alarming . Join Siemens EDA at DVCon 2025 for an exclusive luncheon presentation on February 25th, from 12:30 PM to 1:30 PM , where industry leaders will break down the biggest challenges shaping today’s verification landscape and how Siemens is addressing these challenges.
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Update from the Standards World: Accellera Approves UVM-MS 1.0 Standard
Resource (Verification Horizons Blog) - Feb 10, 2025 by Dennis Brophy
Accellera Systems Initiative approved the Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 standard. This milestone marks a significant advancement in the verification of analog/mixed-signal (AMS) and digital/mixed-signal (DMS) integrated circuits and systems. UVM is widely used around the world but has struggled to work well with designs that have analog/mixed-signal blocks. This is now changed. And it has also given rise to a new logo from Accellera.
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Smart Verification with AI/ML: Smart Regression & Smart Debug
Resource (Slides Download) - Feb 06, 2025 by Austin Mam
Leverage the power of AI and ML! Smart Verification revolutionizes functional verification by using faster engines that complement traditional heuristics with machine learning. Allow engineers to be more productive with advanced creation, analysis, and debugging capabilities, while reducing workloads through predictive technologies that streamline and accelerate the verification process.
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Leveraging Trust and Security Analysis to Meet Design Assurance Requirements
Resource (Slides Download) - Feb 06, 2025 by David Landoll
Learn about the effectiveness of enhancing security verification and improving the robustness of your hardware security verification through detailed explanations and runtime insights. Explore methods to protect against data corruption using formal security verification techniques.
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Integrating the Value of Questa Design Solutions in a Continuous Integration Development Flow
Resource (Slides Download) - Feb 06, 2025 by Walter Gude
Learn the value of Continuous Integration during development and how Questa Design Solutions are ideally suited for implementation in CI flows. Discover the benefits of integrating CI early to enhance RTL quality and streamline development processes.
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Enhancing Productivity in Simulation-Based Functional Verification
Resource (Slides Download) - Feb 06, 2025 by Moses Satyasekaran
Improving productivity has become crucial for efficiently utilizing expensive human and grid resources in the functional verification process. Achieving the "done" state requires more than simulator performance - it demands a strategic focus on optimizing workflows, prioritizing tasks, and leveraging metrics to guide efforts. A productivity-driven approach ensures resources are deployed effectively, accelerating verification closure.
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Breaking the Bottleneck: A Smarter Approach to Semiconductor Verification
Resource (Verification Horizons Blog) - Feb 05, 2025 by Harry Foster
The semiconductor industry is facing a new reality: traditional verification methods can no longer keep pace with the rapid evolution of design complexity. Chiplet-based architectures, 3DICs, and software-defined functionality are pushing verification teams to their limits, amplifying delays, costs, and risk.
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Streamlining FPU Verification with an Alternative to C-reference Model Approaches
Webinar - Feb 05, 2025 by Gerardo Nahum
In this webinar, you will be introduced to the Questa FPU application, explaining how it can quickly detect design inconsistencies and reduce verification time from months to days (based on an easy setup process). You will also learn how Questa Formal Verification IP (VIP) for the AMBA protocol ensures that designs incorporating AMBA adhere strictly to the protocol; all without the need for simulation.
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Streamlining FPU Verification with an Alternative to C-reference Model Approaches
Resource (Slides Download) - Feb 05, 2025 by Gerardo Nahum
In this webinar, you will learn how Questa Formal Verification IP (VIP) for the AMBA protocol ensures that designs incorporating AMBA adhere strictly to the protocol; all without the need for simulation.
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New Advanced Verification Academy Course for Master’s-Level Learning
Resource (Verification Horizons Blog) - Feb 04, 2025 by Harry Foster
Check out our new Functional Verification of Digital Logic course out on the Verification Academy . And check out my promotional video.
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Accellera Sessions at DVCon U.S. 2025
Resource (Verification Horizons Blog) - Jan 31, 2025 by Dennis Brophy
As one of Accellera’s Global Sponsors, Siemens EDA is happy to help shape the Accellera sessions at DVCon U.S and promote its important work on standards. For 2025 there will be five Accellera workshops, three on Monday and two on Thursday. I can’t recall a time when Accellera has had this many sessions covering its expansive work. Two of the workshop sessions come from Accellera initiated standards that are now IEEE standards.
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Breaking the Bottleneck: Overcoming the Verification Productivity Gap 2.0
Resource (Technical Paper) - Jan 31, 2025 by Harry Foster
By integrating AI-driven technologies, we can automate workflows, derive actionable insights and significantly enhance precision in identifying and resolving bottlenecks. This approach will address cross-design-domain interdependencies, alleviate workforce strain and ensure more robust, efficient verification.
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Breaking the Bottleneck: Overcoming the Verification Productivity Gap 2.0
Paper - Jan 31, 2025 by Harry Foster
The semiconductor industry is confronting the Verification Productivity Gap 2.0, characterized by the unique complexities and challenges of the latest semiconductor design technologies. Siemens envisions a transformative solution through connected, data-driven and scalable verification platforms designed to accelerate processes and optimize resource allocation.
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Next-Gen Memory Unlocked: HBM4 and LPDDR6 Verification for High-Performance Computing
Resource (Slides Download) - Jan 30, 2025 by Kamlesh Mulchandani
In this session, discover how Siemens’ Avery Verification IP for HBM4 and LPDDR6 provides a scalable and customizable solution for rigorous protocol compliance and performance testing. Learn how our leading users leverage this VIP to verify their memory controller IP and subsystems, ensuring reliability and readiness for next-generation applications. Guest Speaker: Nidish Kamath from Rambus spoke about Rambus's HBM4 memory controller and the partnership with Avery memory VIP.
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Bridging SoC HW/SW: Co-simulation Challenges and Solutions for X86, ARM, RISC-V Based SoC Teams
Resource (Slides Download) - Jan 30, 2025 by Chris Browy
The Avery VIP team have created solutions in this space that can mix abstraction levels and software as stimulus for our SoC subsystem testbenches. We'll demonstrate how you can benefit from fast, productive verification, while in the simulation phase of your project, with our available Virtual In-Circuit Simulation VIP solutions.
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Accelerating Innovation: PCIe Gen7 Verification for High-Speed Design
Resource (Slides Download) - Jan 30, 2025 by Zhihong Zeng, Jalaj Gupta - Siemens EDA
This session will delve into the advanced features of Avery’s PCIe Verification IP, including dynamic testbench creation, sophisticated traffic generation, error injection, and protocol compliance checks. Discover how this native SystemVerilog/UVM VIP enables rigorous testing of performance, power efficiency, and scalability, ensuring designs meet demands of next-generation PCIe applications. Guest Speaker: Ganesh Venkatakrishnan from Scaleflux presented his experience with the Avery PCIe VIP.
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Breaking Barriers: Ethernet 1.6T, UALink, and UEC Verification for Next-Gen Connectivity
Resource (Slides Download) - Jan 30, 2025 by Pankaj Goel - Siemens EDA
This session introduces Avery Verification IP for Ethernet 1.6T, UALink, and UEC, providing essential tools to verify complex designs for next-generation connectivity. You will gain insights into the key challenges and innovations in Ethernet 1.6T, the latest high-speed Ethernet standard, and learn how Avery's Verification IP accelerates design validation with comprehensive protocol coverage, scalability, and advanced debugging capabilities.
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Mastering UCIe 2.0 Verification: Ensuring Seamless Chiplet Integration
Resource (Slides Download) - Jan 30, 2025 by Luis Rodriguez
This session will focus on the Siemens Avery UCIe Verification IP and the new UCIe2.0 features. Discover its capabilities in dynamic environment creation, including generating complex SiP topologies, portable traffic generation, error injection, and debugging all within a native SystemVerilog/UVM framework.
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An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262
Resource (Slides Download) - Jan 29, 2025 by Jyothy M Jaganathan
Requirements gathering, tracking, safety analysis, and validation all play a critical role; where collaboration between cross-functional teams of safety managers, hardware, software, and verification engineers is needed to guarantee that the chip meets the specified safety standards.