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UVM Connect 2.3.3 Kit

Resource (Tarball) - Dec 11, 2023 by John Stickley

The uvmc-2.3.3 release adds better support for the semantics of the TLM-2.0 base protocol and how it is used in the context of 4-phase transactions.

The UVMC library is provided as a separate, optional package to UVM. You do not need to import the package if your environments do not require cross-language TLM connections or access to the UVM Command API.

UVM Connect 2.3.3 HTML

Resource (Reference Documentation) - Dec 11, 2023 by John Stickley

The UVM Connect library provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog models and components. It also provides a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++).

Multi-Die System Verification with Siemens’s UCIe VIP

Resource (Slides Download) - Dec 07, 2023 by Justin Bunnell

Conventional monolithic SoCs are becoming a bottleneck for power, performance, and area (PPA), creating limitations for Data-intensive applications like high-performance computing (HPC), machine learning (ML) and artificial intelligence (AI), and for hyperscale data centers.

Multi-Die System Verification with Siemens’s UCIe VIP

Webinar - Dec 07, 2023 by Justin Bunnell

In this session, we will introduce you to Siemens EDA's Verification Portfolio and then deep dive into UCIe Verification IP, discussing its key features such as dynamic block-level and SoC level testbench creation, traffic generation, error injection, debug features, and performance monitoring. Siemens Avery UCIe Verification IP is a leading solution in the market, runs on all major simulators and is a native SystemVerilog/UVM class-based Verification IP.

Hierarchical verification flow for FPGA design projects

Resource (Slides Download) - Nov 16, 2023 by Mamma Benmoussa Garsault - Arcys

Limits of verification: learnings from catastrophic system failures

Resource (Slides Download) - Nov 16, 2023 by Philippe Luc

Reducing formal verification runtime in SystemC utilizing modular interface

Resource (Slides Download) - Nov 16, 2023 by Hideki Kazama - Sony

Dusica Glisic - Veriest

Resource (Interview) - Nov 16, 2023 by Dusica Glisic - Veriest

Interview with Dusica Glisic of Veriest about the value of attending Osmosis.

Mihajlo Katona - Veriest

Resource (Interview) - Nov 16, 2023 by Mihajlo Katona - Veriest

Interview with Mihajlo Katona of Veriest about his presentation on combining sim and formal, formal for security, FPGA, and HLS verification, HLS and formal - and advice on starting out with formal.