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2072 Results

  • VA Live - Hudson, MA: Welcome

    Welcome to Verification Academy Live.

  • Redefining Static and Formal Verification

    Recent studies show that first-time silicon success is at an all-time low. It is therefore fair to question whether verification technologies and methodologies deliver the solutions that teams require. Simultaneously, new technologies such as AI yield exciting new opportunities to redefine verification methodologies. Siemens EDA delivers a transformative use of static and formal technologies, empowered by AI and new forms of automation.

  • Redefining Static and Formal Verification

    Siemens EDA delivers a transformative use of static and formal technologies, empowered by AI and new forms of automation. This provides much-needed new verification solutions that improve total user productivity by enabling faster engineers, delivering faster engines and optimizing development by requiring fewer workloads.

  • A Guide to UPF-based Power Intent Verification with Questa One

    This white paper takes a close look at the verification side of UPF with Questa One Sim Power Aware. The focus here is on how to confirm that the described power intent is correctly wired up, tested and functionally sound throughout the design flow. We’ll look at multiple verification approaches and review the tools and technologies offered by Questa One that help design teams close the loop on low-power verification.

  • A Guide to UPF-based Power Intent Verification with Questa One

    This white paper takes a close look at the verification side of UPF with Questa™ One Sim Power Aware. The focus here is on how to confirm that the described power intent is correctly wired up, tested and functionally sound throughout the design flow.

  • DFT Verification: Tackling the Evolving Challenges

    Technological advancement continues as a blistering pace, and the demand for highly reliable systems is paramount across various industries. Safety critical systems and high-performance and heterogenous compute are just a sampling of end markets where customers require the utmost reliability.

  • Streamlining Requirements Traceability using Questa Verification IQ Testplan Author

    In this webinar, you will learn how verification engineers can visualize complex requirement relationships at a glance, identify and address coverage gaps in real-time, and ensure comprehensive requirement implementation and testing.

  • Streamlining Requirements Traceability using Questa Verification IQ Testplan Author

    In this webinar, discover how Questa Verification IQ Testplan Author seamlessly integrates with Application Lifecycle Management tools (such as Siemens Polarion and Jama Connect) to deliver a powerful, collaborative traceability solution that transforms your verification workflow.

  • Solving the Semiconductor Verification Crisis: From Problem to Productivity

    In this webinar, you will discover how a connected, data-driven, and AI-enhanced approach transforms verification into a proactive, scalable system built for 3D ICs, chiplets, and software-defined architectures—delivering higher quality, faster results, and greater productivity across your engineering team.

  • Solving the Semiconductor Verification Crisis: From Problem to Productivity

    The semiconductor industry is facing Verification Productivity Gap 2.0 —a crisis driven by mounting design complexity, growing security demands, and workforce shortages. Traditional verification methods alone can’t keep up. This webinar explores the latest industry trends and challenges shaping functional verification, then introduces  Questa One —Siemens’ smart verification platform engineered to meet these demands head-on.

  • Enhanced Simulation Debugging through Advanced Capabilities of Visualizer

    In this session, you will learn what was holding our Questa Classic users back from adopting Visualizer as their debugger, even though we are sold on the advanced capabilities and performance gains, our strategy to overcome this, and then close out the talk with Visualizer features that have worked well and improvements we hope to see.

  • Enhanced Simulation Debugging through Advanced Capabilities of Visualizer

    This session will start with the introduction of our DUT – the advanced robotic system -- and the corresponding design and verification challenges of constantly reuse code resulting from rapid growth in the last decade.

  • Functional Verification Using Siemens Questa Simulation Technologies

    In this session, you will learn how Tsavorite Scalable Intelligence harnessed the UVM Framework to automate testbench and make-file infrastructure generation and got them started quickly with QuestaSim regressions.

  • Functional Verification Using Siemens Questa Simulation Technologies

    Working at the leading edge of AI Computing, with Chiplet architectures, advanced protocol and memory interfaces, it is essential that our IPs, DUTs, and functional Design Verification teams continue to scale up along with our product line and company. In this session, you will learn how Tsavorite Scalable Intelligence harnessed the UVM Framework to automate testbench and make-file infrastructure generation and got them started quickly with QuestaSim regressions.

  • Shift Left using AutoCheck Formal Verification

    Automated applications with formal verification under-the-hood can truly enable a “shift left”, which will be shown in this presentation on Siemens' Questa AutoCheck. In this case study, we share how this complements our simulation-based RTL verification, as it offers distinct advantages in accelerating bug detection during early RTL development stages.

  • Shift Left using AutoCheck Formal Verification

    In this session we will demonstrate automated applications with formal verification under-the-hood can truly enable a “shift left”.

  • Addressing the Emerging Challenges in DFT Verification with QDX

    The rise of AI accelerators, coupled with multi-die integration and heterogeneous architectures, has driven unprecedented complexity in semiconductor design, making advanced DFT implementations essential to meeting increasingly rigorous quality requirements. In this session we will showcase exciting optimization results obtained by QDX flow in real customer designs.

  • Addressing the Emerging Challenges in DFT Verification with QDX

    In this session we will showcase exciting optimization results obtained by QDX flow in real customer designs.

  • Siemens EDA FuSa Flow for Achieving an ASIL-C Safety Architecture

    This paper demonstrates an integrated, cohesive safety workflow to address the challenges of achieving ISO 26262 compliance and ensure efficient tracking and management of safety-related information, from initial safety analysis to final validation and compliance.

  • Siemens EDA FuSa Flow for Achieving an ASIL-C Safety Architecture

    The ISO 26262 standard underscores the importance of achieving specific random hardware failure rate targets for each automotive safety integrity level and provides a comprehensive framework for assessing, mitigating, and validating random hardware failures. This paper demonstrates an integrated, cohesive safety workflow to address ISO 26262 compliance and ensure efficient tracking and management of safety-related information, from initial safety analysis to final validation and compliance.

  • Breaking the Formal Verification Bottleneck: Faster, Comprehensive Testing for Parameterized Modules

    In the session, we will delve into the P2S methodology, showcase its implementation using our custom compiler, and present a detailed comparison of the P2S approach versus traditional techniques across various design blocks using Questa Formal.

  • Breaking the Formal Verification Bottleneck: Faster, Comprehensive Testing for Parameterized Modules

    This session addresses the challenges of verifying parameterized SoCs designs using Formal Verification. Traditional methods, which involve testing each parameter configuration separately, result in increased test counts, longer runtimes, and incomplete coverage.

  • Accelerating Coverage Closure using Questa Verification IQ Coverage Analyzer & CoverCheck

    In most of the verification flows today, coverage is one of the metrics to determine if verification is completed. The code and functional coverage are two broad categories of coverage which are monitored and tracked for verification sign-off.

  • Accelerating Coverage Closure using Questa Verification IQ Coverage Analyzer & CoverCheck

    This session demonstrates a methodology of how Questa Unreachability (UNR) flow is integrated with Verification IQ (VIQ) tool for accelerating coverage closure. In most of the verification flows today, coverage is one of the metrics to determine if verification is completed. The code and functional coverage are two broad categories of coverage which are monitored and tracked for verification sign-off.

  • Verification of a NAND flash memory controller using UVMF and CDC

    This session will relate to introducing UVM framework and Questa CDC checker for IP development. We'll discuss improvements made through these methods, as well as lessons learned. We'll then cover both the UVM setup, including how the data and control flows were tested.