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DFT's Expanding Role in Software-Driven Silicon: From Structural Test Closure to System-Assurance Evidence

Resource (Paper (.PDF)) - Sep 08, 2026 Harry Foster

The 2026 Siemens EDA and Wilson Research Group Functional Verification Study includes new DFT questions that provide a current-state view rather than longitudinal trend data. The data suggests that DFT verification is increasingly connected with mainstream verification infrastructure, software-driven diagnostics, and silicon-lifecycle evidence.
DFT's Expanding Role in Software-Driven Silicon: From Structural Test Closure to System-Assurance Evidence

Paper - Sep 08, 2026 Harry Foster

Examine the earlier verification of design-for-test logic, integration between DFT and functional verification, accelerated execution, and evolving ownership across engineering teams.
Functional Verification Study Survey Methodology Evolution

Reference - Sep 08, 2026 Harry Foster

Interpreting Long-term Results Across the 2024 Methodology Transition Understand the study’s recruitment transition, the appropriate use of historical comparisons, the treatment of nonresponse, and important considerations for interpreting the survey results.
Functional Verification Study Survey Methodology Evolution

Resource (Reference (.PDF)) - Sep 08, 2026 Harry Foster

Beginning in 2024, the Siemens EDA and Wilson Research Group Functional Verification Study survey shifted from industry-list recruitment to a qualified sample-provider model, creating a break in direct comparability with studies conducted from 2007 through 2022.
2026 Functional Verification Data Atlas

Reference - Sep 08, 2026 Harry Foster

Access the complete study data, including charts, survey-question wording, response bases, IC/ASIC and FPGA breakouts, nonresponse information, and data-quality notes.
2026 Functional Verification Data Atlas

Resource (Reference (.PDF)) - Sep 08, 2026 Harry Foster

A chart-level reference to selected 2026 Functional Verification Study findings. It is intended for lookup and citation support rather than long-form interpretation.
Why Agentic AI Could Redefine the Future of Design and Verification

Resource (Verification Horizons Blog) - Aug 31, 2026 Harry Foster

The semiconductor industry is no stranger to transformation. New architectures, new methodologies, and new levels of automation have repeatedly changed what engineering teams can accomplish. But the shift happening now feels different.
The Verification Problem is Changing. Are We Asking the Right Questions

Resource (Verification Horizons Blog) - Aug 24, 2026 Harry Foster

There has never been a more exciting time to be working in semiconductors. Silicon is rapidly becoming the intelligence underneath almost everything around us from AI infrastructure and autonomous vehicles to factories, robots, connected cities, and systems operating in space. As silicon takes on more intelligence, more autonomy, and more responsibility, however, something else is happening: The verification problem is changing.
Questa One VeriThreader: Rethinking Verification Traceability for Modern Systems

Resource (Paper (.PDF)) - Aug 14, 2026 Jake Wiltgen

Download this white paper to learn why traditional approaches to verification traceability are no longer enough for modern development and how a lifecycle-wide approach can help improve visibility, strengthen traceability, and support better understanding of verification consequences across complex systems.
Questa One VeriThreader: Rethinking Verification Traceability for Modern Systems

Paper - Aug 14, 2026 Jake Wiltgen

Verification is no longer a localized activity. It is a lifecycle-wide discipline that must connect evidence from concept to implementation. Traditional verification leaves verification activities disconnected across tools, organizations, and handoff points. This reduces visibility, complicates impact analysis, weakens auditable traceability, and limits reuse of verification knowledge.
PCIe 8.0 over UCIe 3.0: Bringing a Proven Protocol into the Chiplet Era

Resource (Paper (.PDF)) - Aug 12, 2026 Prashant Dixit

In this paper, you will learn that PCIe 8.0 over UCIe 3.0 paves a practical roadmap to carry the industry’s most established I/O protocol into the chiplet era. For designers building AI, HPC, storage, and heterogeneous compute platforms, this combination enables silicon disaggregation without abandoning standards-based interoperability.
PCIe 8.0 over UCIe 3.0: Bringing a Proven Protocol into the Chiplet Era

Paper - Aug 12, 2026 Prashant Dixit

As architectures move from monolithic SoCs to chiplet-based designs, the value of PCIe remains high, yet conventional PCIe implementations board-oriented assumptions are no longer ideal for short-reach, in-package communication. UCIe standardizes die-to-die communication within a package and allows PCIe traffic to traverse chiplet boundaries with seamless interoperability over standardized interconnects.
Agentic AI and the Rise of the Design and Verification Scientist

Conference - Jul 26, 2026 Chandu Challapalli

This session explores how agentic AI can address both challenges. Autonomous systems that reason, plan, and adapt across the chip development lifecycle don't just accelerate workflows, they dissolve boundaries between creation and validation entirely.
Full Spectrum Equivalence Checking: From C++ to the FPGA Bitstream

Webinar - Jul 22, 2026 Kevin Urish

In this session, we will equip you with comprehensive solutions to tackle current and emerging verification trends and compliance requirements for FPGA designs including optimizing verification productivity and quality and streamlining your high-level language verification flow for FPGA designs.
Full Spectrum Equivalence Checking: From C++ to the FPGA Bitstream

Resource (Slides (.PDF)) - Jul 22, 2026 Kevin Urish

In this session, you will learn how to leverage Siemens and industry partner solutions to leverage your verified high-level language design and extend that verification through to the FPGA bitstream.
When Thousands of RDC Violations aren’t Real: Making RDC Verification Smarter

Resource (Verification Horizons Blog) - Jul 17, 2026 Reetika

Imagine opening your latest reset domain crossing (RDC) report after a long overnight verification run. The analysis completes successfully. That’s great, but then you see the numbers: 50,000 RDC violations! Your first thought shouldn’t be: “The design is broken.” It should be: “How many of these are actually real?”
Discover What’s Next: Siemens EDA at DAC 2026

Resource (Verification Horizons Blog) - Jul 14, 2026 Harry Foster

The semiconductor industry is entering a new era. AI is changing not only the chips we design, but how we design them. 3D IC and heterogeneous integration are redefining what constitutes a “system.” And as products become increasingly software-defined, the boundaries between silicon, hardware and software continue to disappear. That’s why I’m particularly excited about this year’s Design Automation Conference (DAC) in Long Beach.
From False Alarms to Real Insights: Refining RDC to Catch Missed STA Scenarios

Paper - Jul 01, 2026 Reetika

This paper introduces a refined verification methodology that leverages intelligent filtering and classification to separate true hazards from safe crossings. By cutting through the noise, the approach not only reduces verification effort but also shortens closure time, enabling faster, more confident sign-off. Ultimately, this work demonstrates how smarter RDC verification can transform a traditionally tedious process into an efficient and reliable path to design quality.
Verification Academy 2026 Webinar Round-Up

Resource (Verification Horizons Blog) - Jun 15, 2026 Dennis Brophy

It’s hard to believe, but we’re already almost halfway through 2026! Time flies when you’re innovating, and here at Siemens, we’ve been busy bringing you a fantastic lineup of webinars to keep you at the forefront of technology. We’ve covered a lot of ground in the first half of the year, diving deep into everything from advanced verification techniques to the exciting world of AI/ML design.
Resolve Metastability: Improve Your Clock-Domain Crossing Verification with Questa CDC

Resource (Slides (.PDF)) - Jun 10, 2026 Ratko Raicki

In this webinar, we will explain the major elements of CDC verification. With our differentiating features, we will highlight unique verification techniques in Questa, where verification of large numbers of CDC paths can be achieved easily.
Resolve Metastability: Improve Your Clock-Domain Crossing Verification with Questa CDC

Webinar - Jun 10, 2026 Ratko Raicki

Do you have issues in fully verifying clocks in your design? Do you find CDC (clock-domain crossing) verification tasks daunting due to their complexities? Questa CDC offers a powerful, integrated approach to improve these verification processes. In this webinar, we will explain the major elements of CDC verification. With our differentiating features, we will highlight unique verification techniques in Questa, where verification of large numbers of CDC paths can be achieved easily.
Questa One VIQ Smart Verification

Resource (Slides (.PDF)) - Jun 09, 2026 Austin Mam

This session will explore Verification IQ (VIQ) and how it brings AI/ML-driven intelligence into the verification flow. Attendees will learn how VIQ leverages data from simulation, formal, and coverage to provide actionable insights such as predictive failure analysis, coverage guidance, and regression optimization. This session will demonstrate how smart verification enables improved productivity and a more efficient path to verification closure.
Questa One SFV Trust and Assurance

Resource (Slides (.PDF)) - Jun 09, 2026 David Landoll

In this session, you will learn about the effectiveness of enhancing security verification and improving the robustness of hardware security verification through detailed explanations and runtime insights. Explore methods to protect against data corruption using formal security verification techniques.
BAE: Automation of FPGA Development Process using Jenkins Continuous Integration and Continuous Deployment

Resource (Slides (.PDF)) - Jun 09, 2026 Laks Vanchinathan - BAE

This session presents an implementation of a Continuous Integration/Continuous Deployment (CI/CD) pipeline for FPGA development using Jenkins, an opensource automation server. The CI/CD pipeline automates build, test, and deployment of code changes, standardizing best practices in design and verification workflows.
From Algorithm to UVM: Accelerating Design Verification with MATLAB, Simulink, and HDL Verifier

Resource (Slides (.PDF)) - Jun 09, 2026 Andrew Santos - MathWorks

This session will show how MathWorks tools — MATLAB®, Simulink®, and HDL Verifier™ — enable model-based design techniques to accelerate design verification. Attendees will see how executable reference models and reusable testbench components can be created and run natively in Siemens Questa, enabling shift-left verification across co-simulation, DPI-based testbenches, and UVM/UVMF environments.