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Verifying Chiplet Interconnects at Scale: UCIe® 3.0
Resource (Slides (.PDF)) - Feb 04, 2026 by Luis Rodriguez
This session highlights what’s new in UCIe 3.0 and explains how Avery UCIe Verification IP enables faster bring-up, deeper protocol coverage, and reduced risk by validating compliance, corner cases, and system-level behavior—helping teams confidently deliver robust chiplet-based silicon. Guest Presenter: Jie Ding – Ayar Labs
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Verifying Future Accelerator Interconnects: UALink™ Verification IP and Why UALink Matters
Resource (Slides (.PDF)) - Feb 04, 2026 by Jalaj Gupta
This session highlights the importance of UALink and the verification challenges it introduces and shows how Avery UALink Verification IP delivers immediate value by accelerating bring-up, improving coverage of protocol corner cases, and reducing overall verification risk and time-to-market. Guest Presenter: Saro Kalinagasamy – Astera Labs
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Achieving Mathematical Certainty in Design Verification with Formal
Paper - Jan 31, 2026 by Nicolae Tusinschi
This paper provides a comprehensive exploration of formal verification methodologies, techniques, and best practices for hardware design engineers and verification specialists. Formal verification employs mathematical analysis to prove correctness across all possible scenarios. This exhaustive approach is particularly critical in safety-critical systems, high-reliability applications, and complex digital designs where corner-case bugs can have catastrophic consequences.
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Achieving Mathematical Certainty in Design Verification with Formal
Resource (Paper (.PDF)) - Jan 31, 2026 by Nicolae Tusinschi
The future of hardware verification lies in the intelligent combination of formal verification, simulation, and other verification methodologies, each applied where it provides the most value. By mastering the techniques presented in this whitepaper, verification engineers position themselves to meet the verification challenges of increasingly complex hardware designs.
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Cut Weeks From Debug: Rapid First – Level Bug Hunting with Inspect and Check X
Webinar - Jan 29, 2026 by Bobana Brzacki
In this webinar we introduce intuitive 'push-button' bug-hunting tools, Inspect and Check X, designed to transform your verification process. Join us for a practical deep dive into their core functionalities, demonstrating their efficient workflow from initial setup to insightful results analysis. You will gain a clear understanding of how these powerful solutions empower them to rapidly identify and resolve first-level design bugs, ensuring a more robust design and accelerated time-to-market.
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Cut Weeks From Debug: Rapid First – Level Bug Hunting with Inspect and Check X
Resource (Slides (.PDF)) - Jan 29, 2026 by Bobana Brzacki
In this webinar, you will gain a clear understanding of how these powerful solutions empower them to rapidly identify and resolve first-level design bugs, ensuring a more robust design and accelerated time-to-market
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Supercharge Your CDC & RDC Analysis with the Power of AI/ML
Webinar - Jan 28, 2026 by Farhad Ahmed
One of the biggest challenges in CDC/RDC verification is managing the complexity and time-consuming nature of identifying and resolving violations. CDC/RDC Assist addresses this challenge by leveraging AI/ML to automate and accelerate causality analysis. In this webinar, you will learn how to streamline CDC/RDC verification using machine learning to automate violation detection and resolution.
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Supercharge Your CDC & RDC Analysis with the Power of AI/ML
Resource (Slides (.PDF)) - Jan 28, 2026 by Farhad Ahmed
In this webinar, you will learn how to streamline CDC/RDC verification using machine learning to automate violation detection and resolution.
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Simulating CDC Reconvergence: Validating Robustness with Questa One Sim's Metastability Injection
Webinar - Jan 21, 2026 by Sunil Sahoo
This webinar will delve into Questa One Sim’s groundbreaking metastability injection capability , a pivotal advancement that brings the critical aspect of non-deterministic delay validation directly into the simulation realm. We will demonstrate how this new feature enables designers to actively model and inject varying metastability delays into synchronizer paths, allowing for rigorous verification of sequential reconvergence logic.
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Simulating CDC Reconvergence: Validating Robustness with Questa One Sim's Metastability Injection
Resource (Slides (.PDF)) - Jan 21, 2026 by Sunil Sahoo
In this webinar, you will learn how to gain unparalleled confidence in your design’s resilience to metastability effects, ensuring robust functional correctness and accelerating verification closure for complex multi-clock SoCs.
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BUGGED OUT Podcast - Episode 3: Chandu Challapalli
Resource (Podcast) - Jan 20, 2026 by Harry Foster
Harry Foster talks with Chandu Challapalli, Senior Management Director at Siemens EDA, about why timing constraints must be treated as first-class verification assets. Drawing on insights from his white paper, A Guide to SDC-based Timing Intent Verification with Questa One , Chandu explains how automated SDC verification uncovers hidden timing risks, balances under- and over-constraining, and shifts timing validation earlier in the design cycle.
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New Innovative Way to Functionally Verify Heterogeneous 2D/3D Package Connectivity
Resource (Paper (.PDF)) - Jan 16, 2026 by Jin Hou
The heterogeneous integration of multiple ICs in a single package along with high-performance, high bandwidth memory is critical for many high-performance computing applications. After everything has been heterogeneously integrated and packaged, such designs feature complex connectivity with many hundreds of thousands of connections, making it extremely challenging to verify the correctness of the connections.
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New Innovative Way to Functionally Verify Heterogeneous 2D/3D Package Connectivity
Paper - Jan 16, 2026 by Jin Hou
This paper introduces a new way to functionally verify packaging connectivity using formal verification that can exhaustively verify all interconnections between IC blocks. The flow is automatic for all steps, from creating connectivity specifications to verifying packaging output connectivity. The automatic parallel algorithms on the compute grid can verify huge numbers of connections in minutes or even seconds. The script for the flow is simple and only takes a few minutes to set up.
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Formal Verification Made Simple: A Practical Guide for FPGA Designers
Webinar - Jan 15, 2026 by Bobana Brzacki
In this webinar we will demystify formal verification and show you how SFV fits naturally into your existing FPGA design flow. Whether you're working on control logic, interfaces, or complex state machines, you'll discover how formal can catch bugs that simulation misses - early, automatically, and exhaustively.
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Formal Verification Made Simple: A Practical Guide for FPGA Designers
Resource (Slides (.PDF)) - Jan 15, 2026 by Bobana Brzacki
If you're an FPGA designer who's heard that formal verification is "too complex" or "not for FPGA workflows," this session will change your mind.
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Constrained Randomization and Functional Coverage in Questa One Sim with UVVM
Webinar - Jan 14, 2026 by Abdelrahman Tharwat
In this webinar, we’re excited to showcase the latest cutting-edge features of Questa One Sim, with UVVM (Universal VHDL Verification Methodology) . Learn how the newly added support for constrained randomization with multi-variable capabilities allows you to dynamically generate randomized, UVVM-compliant stimuli that address even the most intricate design constraints, helping you explore vast verification scenarios efficiently and effectively.
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Constrained Randomization and Functional Coverage in Questa One Sim with UVVM
Resource (Slides (.PDF)) - Jan 14, 2026 by Abdelrahman Tharwat
This webinar is your gateway to unlocking a streamlined and enhanced verification experience by leveraging Questa One Sim advanced features in tandem with UVVM.
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System Verifier
Resource (Verification Horizons Blog) - Jan 05, 2026 by Julie Weber
Software-defined, AI-controlled systems are transforming industries—from aerospace and defense to automotive and industrial automation. But with this transformation comes complexity: as software workloads grow, electronic systems face higher risks of non-deterministic failure mechanisms. Traditional engineering methods and tools are no longer enough to anticipate these risks or prevent “integration hell.”
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BUGGED OUT Podcast - FutureCast 2026: Part 2
Resource (Podcast) - Dec 16, 2025 by Harry Foster
Harry Foster returns with Part 2 of this special holiday edition of BUGGED OUT , continuing the exploration of how silicon and verification are rapidly evolving. In this episode, Harry looks at the forces accelerating change — from rising specialization and data-movement bottlenecks to growing power and security pressures that now shape system behavior. To dive deeper into these themes, you can also download the companion paper — The Future of Semiconductors: Engineering in the Convergence Era .
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Formal Verification of Synthesizable C++/SystemC Designs
Resource (Paper (.PDF)) - Dec 12, 2025 by Vlada Kalinic
In this paper, you will learn that HLV formal tools from Siemens can be used to clean SystemC/C++ design code before running HLS as well as to verify the functionality of the SystemC designs with SVA assertions. Steps in this flow include using the GUI counter-example capability to debug failures on the SystemC/C++ designs and focusing on the reachable parts by using the increase coverage solution to detect unreachable code.
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Formal Verification of Synthesizable C++/SystemC Designs
Paper - Dec 12, 2025 by Vlada Kalinic
Formally checking generated RTL can be difficult to analyze as errors cannot be correlated to the HLS source code. Questa HLV can help overcome this challenge with high-level verification. Siemens offers several apps to verify and clean C++ HLS code before running HLS and then check the equivalency between C++ and RTL.
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The Future of Semiconductors: Engineering in the Convergence Era
Resource (Paper (.PDF)) - Dec 09, 2025 by Harry Foster
The semiconductor industry is entering a convergence era where silicon, software, physics, packaging, security, AI, and power constraints all intertwine. Device scaling still matters but architecture, integration, verification, and automation will define the industry’s trajectory. Organizations that embrace this cross-domain, lifecycle-oriented mindset will define the next decade.
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The Future of Semiconductors: Engineering in the Convergence Era
Paper - Dec 09, 2025 by Harry Foster
Reflections from inside an industry undergoing its biggest transformation in decades. The semiconductor industry is entering a convergence era where silicon, software, physics, packaging, security, AI, and power constraints all intertwine. Device scaling still matters but architecture, integration, verification, and automation will define the industry’s trajectory. Organizations that embrace this cross-domain, lifecycle-oriented mindset will define the next decade.
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FutureCast 2026: A Special Holiday Edition of BUGGED OUT
Resource (Verification Horizons Blog) - Dec 09, 2025 by Harry Foster
As another year closes, the semiconductor industry finds itself in a moment of transition—one where the pace of innovation is accelerating faster than many expected. Chip architectures are evolving, system boundaries are shifting, and verification continues expanding into new territory we couldn’t have imagined even a decade ago. And like many of you, I find the end of the year to be a natural time to pause, look back, and ask a simple but important question: Where is all of this heading?
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BUGGED OUT Podcast - FutureCast 2026: Part 1
Resource (Podcast) - Dec 04, 2025 by Harry Foster
Harry Foster kicks off a special two-part holiday edition of BUGGED OUT with a look at the rapidly shifting landscape of modern silicon. Harry also shares his predictions for where the semiconductor and verification ecosystem is headed in 2026 — and beyond. To dive deeper into these themes, you can also download the companion white paper— The Future of Semiconductors: Engineering in the Convergence Era .