Enhanced Randomization and Functional Coverage: Make Better VHDL Testbenches
In this session, you will learn that UVVM’s advanced and optimized randomization and functional coverage was developed in cooperation with ESA (European Space Agency). In UVVM, understanding and readability of these features have been taken to a new level and UVVM also introduces functionality not previously available for VHDL testbenches. The user threshold is far lower than SystemVerilog and makes it easy for VHDL designers to use this advanced functionality.
