Combined Formal and Functional Verification Approach for Digitally Controlled Analog Frontend
In this session, we present a fusion of formal and dynamic verification methods we applied in a mixed signal IC project. The challenge for DV verification team was to select the most suitable verification method. The idea here was to save time on top-level integration where only integration of one sub-system is required. With this experience, we learned that formal verification can significantly speed-up design bug discoveries and improve functional definitions in the system specification.
