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Using Strong Types in SystemVerilog Design and Verification Environments

Resource (Paper (.PDF)) - Feb 28, 2019 by Dave Rich

In this paper, you will learn that a strongly-typed language does not allow operations on data that are of incompatible types. Having strong types, as in VHDL, helps define intent and avoid errors, but is much more verbose.
Ten Rules to Successfully Deploy Formal

Article - Feb 25, 2019 by Dr. Ashish Darbari

About four years ago I gave a couple of talks on the myths surrounding formal. Although, formal has seen more adoption since then, we have a long way to go before it is recognized as a mainstream technology used throughout design and verification. I still see some of these myths clouding the judgement of end users and their managers.
Formal Apps Take the Bias Out of Functional Verification

Article - Feb 25, 2019 by Bill Au

When we spend hours, days, or even weeks putting our hearts and minds into creating something, we have a tendency to emphasize its strengths and minimize its weaknesses. This is why verification engineers have a blind spot for their own verification platforms. This blind spot, or bias, often leads to overlooking those areas where bugs may lurk, only to emerge at the worst possible time when errors are most costly and take longer to fix.
Simplifying Assertion Validation Using UVM Callbacks

Article - Feb 25, 2019 by Arushi Jain - Siemens EDA

An assertion is a conditional statement that indicates the incorrect behavior of a design by flagging an error and thereby catching bugs. Assertions are used for validating a hardware design at different stages of its life-cycle, such as formal verification, dynamic validation, runtime monitoring, and emulation.
Effective Elements Lists and the Transitive Nature of UPF Commands

Article - Feb 25, 2019 by Progyna Khondkar

In this article, we provide a simplistic approach to find inherent links between UPF commands-options through their transitive nature. We also explain how these inherent features help to foster and establish exact relationships between UPF and DUT objects in order to develop UPF for power management and implementation as well as conduct power aware verification.
Selecting a Portable Stimulus Application Focal Point

Article - Feb 25, 2019 by Matthew Ballance

As designs, especially System on Chip designs, have become more complex, the need for generated good, automated stimulus across the verification spectrum has increased. Today, the need for verification reuse and automated stimulus is clearly seen from block to subsystem to SoC-level verification.
Choosing a Format for the Portable Stimulus Specification

Resource (Paper (.PDF)) - Feb 22, 2019 by Matthew Ballance

This white paper discusses portable stimulus, the industry’s solution for verification portability up and down the design hierarchy and across platforms.
Part 10: IC/ASIC Language and Library Adoption Trends

Resource (Verification Horizons Blog) - Feb 14, 2019 by Harry Foster

In my previous blog ( click here ), I examined IC/ASIC project verification technology adoption trends. In this blog I plan to discuss various IC/ASIC language and library adoption trends.
Part 9: IC/ASIC Verification Technology Adoption Trends

Resource (Verification Horizons Blog) - Feb 05, 2019 by Harry Foster

In my previous blog ( click here ), I focused on IC/ASIC design project resource trends. In this blog I examine IC/ASIC project verification technology adoption trends.
Low Power Verification Forum

Webinar - Feb 05, 2019 by Gordon Allan

In this session, you will be introduced to new and unique low power coverage methodologies that enable designers to verify and track how well they have tested their power management architecture.
Part 8: IC/ASIC Resource Trends

Resource (Verification Horizons Blog) - Jan 29, 2019 by Harry Foster

In my previous blog ( click here ), I presented trends related to various aspects of design to illustrate growing design complexity. In this blog, I plan to discuss the growing IC/ASIC project resource trends resulting from growing design complexity.
Industry Advancements Required to Close the Power Management Verification Gap

Webinar - Jan 28, 2019 by Sriram Hariharan

In this session, you will learn how Qualcomm overcomes their power verification challenges and how they utilize power aware verification techniques.
Deploying a Metrics Driven Low Power Methodology for Your RTL IP

Webinar - Jan 28, 2019 by Qazi Ahmed

In this session, you will learn how PowerPro is a single solution for RTL audit, power optimization, estimation and exploration.
Low Power Verification & Analysis with Emulation

Webinar - Jan 28, 2019 by Shantanu Samant

In this session, you will learn how Emulation techniques can be used for low power verification including power analysis and power estimation.
Productive Low Power Debug Across All Engines and Flows

Webinar - Jan 28, 2019 by Gordon Allan

In this session, we will answer the top nine questions asked for debugging low power in your design.
Accelerating Verification through Verification IP, Configurator and UVM Framework

Resource (Slides (.PDF)) - Jan 24, 2019 by Sharath Kannareddy
Making Verification Fun Again

Resource (Slides (.PDF)) - Jan 24, 2019 by Jonathan Craft
Verification Acceleration for FPGA Designs with Matlab

Resource (Slides (.PDF)) - Jan 24, 2019 by Jerry Grula - Siemens EDA
Welcome & Overview

Resource (Slides (.PDF)) - Jan 24, 2019 by Harry Foster
ASIC & FPGA SoC Functional Verification Trends

Resource (Slides (.PDF)) - Jan 24, 2019 by Harry Foster
Part 7: IC/ASIC Design Trends

Resource (Verification Horizons Blog) - Jan 22, 2019 by Harry Foster

In my previous blog ( click here ), I focused on FPGA design and verification trends. Now my plan is to shift the focus in this series of blogs from FPGA trends to IC/ASIC trends. And specifically in this blog, I present trends related to various aspects of design to illustrate growing design complexity.
Part 6: FPGA Verification Language and Library Adoption Trends

Resource (Verification Horizons Blog) - Jan 15, 2019 by Harry Foster

In my previous blog ( click here ) I discussed FPGA verification techniques and technologies adoption trends, as identified by the 2018 WRG study. In this blog, I’ll present FPGA design and verification language adoption trends. It is not uncommon for FPGA projects to use multiple languages when constructing their RTL and testbenches. This practice is often due to legacy code as well as purchased IP.
Part 5: FPGA Verification Technology Adoption Trends

Resource (Verification Horizons Blog) - Jan 07, 2019 by Harry Foster

In my previous blog ( click here ) I discussed verification effort trends specifically focused on where FPGA design and verification engineers spend their time. In this blog I present verification techniques and technologies adoption trends, as identified by the 2018 Wilson Research Group study.
Part 4: FPGA Verification Effort Trends (Continued)

Resource (Verification Horizons Blog) - Jan 02, 2019 by Harry Foster

In my previous blog ( click here ) I discussed verification effort trends in terms of project time spent in verification, as well as increasing headcount as indicated by the rising mean peak number of design and verification engineers working on FPGA projects. In this blog I continue the discussion of FPGA verification effort trends by looking at where engineers spend their time.
How to Unearth Deep Bugs Faster and Cheaper Using Formal Bug Hunting Techniques

Webinar - Dec 23, 2018 by Mark Eslinger

In this session, you will learn how to leverage formal analysis to find and fix as many functional bugs as possible, ultimately improving the quality of your end-product, and lowering the risk of re-spins.