Upcoming Webinar

Simulating AMD’s next-gen Versal Adaptive SoC devices using QuestaSim

Wednesday, July 24th - 8:00 AM US/Pacific

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  1. Introduction

    With the number of clock domains increasing in today’s complex ASIC designs, the ability to thoroughly verify clock domain crossings (CDC) has become even more important. As in functional verification, to ensure CDC issues are thoroughly verified, a comprehensive test plan is essential. Based on our experience working with many customers, we developed a five-step planning process for CDC verification.

    After having a CDC test plan, an effective CDC verification methodology should include structural, protocol, and metastability verification. This ensures that CDC signals are handled reliably at the design stage, avoiding costly respins after they are fabricated. We will outline how these are applied to block-level and top-level RTL modules. We will describe a few common CDC violations and the techniques used to determine whether they are real design issues or not. Finally, we will summarize and highlight the results of applying this methodology to a few designs.


    When a single-bit CDC signal is sampled by a register in a different clock domain, the output of the register can change at any time with respect to the clock of the receiving register. In hardware, if the value of the CDC signal changes during the register’s setup or hold time, the register may output a voltage level between 0 and 1. When this occurs, the register is said to be metastable [1, 2]. The output of a metastable register will eventually settle to either 0 or 1. However, which value the register settles to is, for all practical purposes, unpredictable.

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