Search Results

Advanced Search

2419 Results

Detecting Security Vulnerabilities in a RISC-V® Based System-on-Chip

Article - Mar 01, 2020 Dr. Nicole Fern - Tortuga Logic

Modern electronic systems are complex, and economics dictate that the design, manufacturing, testing, integration and deployment of Application Specific Integrated Circuits (ASICs), System on Chips (SoCs) and Field Programmable Gate Arrays (FPGAs) span companies and countries. Security and trust in this diverse landscape of 3rd party IP providers, processor vendors, SoC integrators and fabrication facilities, is both challenging and introduces security risks.
Formal Verification of RISC-V® Processors

Article - Mar 01, 2020 Dr. Ashish Darbari

The verification of modern-day processors is a non-trivial exercise, and RISC-V® is no exception. In this article, we present a formal verification methodology for verifying a family of RISC-V® “low-power” processors. Our methodology is both new and unique in the way we address the challenges of verification going beyond just functional verification.
Part 10: IC/ASIC Language and Library Adoption Trends

Resource (Verification Horizons Blog) - Jan 20, 2020 Harry Foster

In this blog, I plan to discuss various IC/ASIC language and library adoption trends. Figure 10-1 shows the aggregated adoption trends for languages used to create RTL designs across all market segments and all regions of the world. We see continual interest in SystemVerilog for RTL creation.
Tackling Random Blind Spots with Strategy-Driven Stimulus Generation

Article - Jan 07, 2020 Matthew Ballance
Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF

Article - Jan 07, 2020 Joe Hupcey
Low Power Apps: Shaping the Future of Low Power Verification

Article - Jan 07, 2020 Verification News
Managing and Automating HW/SW Tests from IP to SoC

Article - Jan 07, 2020 Matthew Ballance
Reusable UPF: Transitioning from RTL to Gate Level Verification

Article - Jan 07, 2020 Verification News
Unleashing Portable Stimulus Productivity with a PSS Reuse Strategy

Article - Jan 07, 2020 Matthew Ballance
Results Checking Strategies with Portable Stimulus

Article - Jan 07, 2020 Matthew Ballance
Push-Button FMEDAs for Automotive Safety: Automating a Tedious Task

Paper - Dec 15, 2019 Doug Smith

In this paper you will learn that by automating the tedious task of FMEDA creation, using the tools and methods described in this paper, you have more time to focus on exploring your design’s safety readiness and figuring out how you can better safety-harden your design. If you need help starting, automating, or performing your functional safety process, Siemens EDA Consulting services is available today to help you successfully bring your automotive design to market.
Push-Button FMEDAs for Automotive Safety: Automating a Tedious Task

Resource (Paper (.PDF)) - Dec 15, 2019 Doug Smith

FMEDAs are used to determine each safety goal’s diagnostic coverage, which in turn determines if the design will meet the targeted ASIL requirements. However, if you have ever written an FMEDA, you know how tedious a task this can be. In this paper, we share a push-button solution for creating and automating the FMEDA process.
Achieving Functional Safety for Autonomous Vehicle SoC Designs

Paper - Dec 06, 2019 Jake Wiltgen

Vehicle architecture design is converging to a more centralized, domain-processing model. These domain-based processors are the new key differentiator for car buyers. Domains such as automated driving, vehicle connectivity and mobility solutions that rely on sophisticated AI algorithms and intense computations require SoCs optimized for the specific challenges of each application.
Why Hardware Emulation Is Necessary to Verify Deep Learning Designs

Article - Dec 03, 2019 Jean-Marie Brunet

There is no doubt that computers have changed our lives forever. Still, as much as computers outperform humans at complex tasks such as solving complex mathematical equations in almost zero time, they may underperform when solving what humans can do easily — image identification, for instance. Anyone in the world can identify a picture of a cat in no time at all. The most powerful PC in the world may take hours to get the same answer.
Deadlock Prevention Made Easy with Formal Verification

Article - Dec 03, 2019 Dr. Jeremy Levitt

You are about to go into a planning meeting for a new project when you get a call from one of your company’s Customer Advocate Managers: a product that you worked on just started shipping in volume, and there are a growing number of field reports that the system randomly freezes-up after a few weeks in operation. While a soft reset “works,” it will run anywhere from 5 to 10 days before it has to be rebooted again.
Exercising State Machines with Command Sequences

Article - Dec 03, 2019 Matthew Ballance

Almost every non-trivial design contains at least one state machine, and exercising that state machine through its legal states, state transitions, and the different reasons for state transitions is key to verifying the design’s functionality. In some cases, we can exercise a state machine simply as a side-effect of performing normal operations on the design.
Designing A Portable Stimulus Reuse Strategy

Article - Dec 03, 2019 Matthew Ballance

The PSS language was designed with the requirements of test intent reuse, and automated test creation in mind. The requirement to allow test intent to be reused across a variety of very different platforms drove the PSS language to enable a clean and clear distinction between test intent and test realization, as shown in Figure 1. In a PSS description, test intent specifies the high-level view of what behavior is to be exercised.
Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon

Article - Dec 03, 2019 Kurt Takara

In this article, we will discuss the difficulties encountered with traditional CDC protocol verification methodologies and present a complete methodology to overcome the current challenges.
UVMC 2.3.2 Library

Resource (Reference Documentation) - Nov 15, 2019

v2.3.2 The UVM Connect library provides TLM1 and TLM2 connectivity between SystemC and SystemVerilog models and components. It also provides a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++). This document provides a user guide to the UVM-Connect API package itself as well as a primer on TLM-2.0 usage in general.
UVM Connect 2.3.2 Kit

Resource (Tarball) - Nov 14, 2019 John Stickley
UVM Connect 2.3.2 Primer

Resource (Reference Documentation) - Nov 14, 2019 John Stickley
UVM Connect 2.3.2 Primer

Resource (Reference Documentation) - Nov 14, 2019 John Stickley
UVM Connect 2.3.2 HTML

Resource (Reference Documentation) - Nov 14, 2019 John Stickley
UVM Connect 2.3.2 Primer

Resource (Reference Documentation) - Nov 14, 2019 John Stickley
Formal Property Checking

Track - Oct 14, 2019 Mark Eslinger

Questa Property Checking (PropCheck) supports general assertion-based formal verification to ensure that the design meets its specific functional requirements.