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New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

March 14th @ 8:00 AM US/Pacific

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    Authors: Durgesh Prasad - Mentor, A Siemens BusinessJitesh Bansal - Mentor, A Siemens BusinessMadhur Bhargava - Mentor, A Siemens Business Abstract: United Power Format (UPF) is used in a design to specify the power intent of the design. The UPF file is used at all the stages in the verification starting from RTL verification to GLS to place & route stages however it is often the case that UPF needs to be modified at next verification stage. For example UPF at RTL level needs to be modified to be used at GLS level due to design-hierarchy changes, cell placements and cell connections. This creates problem of managing different UPFs at various stages, checking their equivalence to make sure the consistency. In this paper we want to highlight all the differences between an RTL UPF and a GLS UPF. We would also propose a methodology to write RTL UPF in such a way that minimal changes are required during gate level power verification. Introduction: Today’s chips require a sophisticated verification methodology. The normal trend is to verify the chip at multiple level starting from verification at RTL then to Gate Level and further down to place & route netlist. RTL is the most abstract level of describing the design and provides very fast verification turnaround but at the same time it is not able to catch all the issues so designers tend to move to Gate level simulation. Gate level simulation overcomes the limitations of static-timing analysis and is increasingly being used because of complex timing checks at 40nm and below, design for test (DFT) insertion at gate level and low power considerations. Other reasons for running gate level simulation are reset verification, X optimism in RTL and basic heartbeat tests. The next step in chip design cycle is place & route in which the tool extract the components and nets from the netlist, place the components on the target device, and interconnect the components using the specified interconnections. After the place and route verification process is complete, the designer has an implementation of the design in the target technology. Now a day’s one of the very important aspect of verification is the low-power. Earlier power decisions were only taken at the place & route stage which was very late and any bug found in the design at that stage would take huge time to fix. To overcome this problem designer started applying power aspect very early in the design cycle starting at RTL itself. UPF emerged as the most accepted format to represent power intent of the design. Power Intent is specified in the UPF file and it is then applied at every stage of design cycle, starting at RTL level, then at gate-level and finally at place & route level too. However one of the main concern in application of power-intent is that UPF needs to be refined/modified up to some extent at every stage to keep it compatible with the netlist. This creates different flavors of UPF which lacks consistency and creates maintenance problem. The motivation behind this paper is to explain the challenges why UPF needs to be changed when designer shifts from RTL to gate level verification and how we can write a better UPF at RTL itself so that it requires minimal or no changes when it goes to Gate Level netlist. To understand these reasons, first we need to understand the relevant basics of UPF. View & Download: Read the entire Reusable UPF: Transitioning from RTL to Gate Level Verification technical paper | Poster | Presentation Source: DVCon US 2018