Verification Academy

Topic	Replies	Views	Activity
Wait_for_state() in a static module doesn't work as expected UVM UVM-phase-methods , UVM_PHASE , phase , Cookbook-Phasing , UVM-phases , Related-to-UVM-phases , phasing , Phasing-within-a-static-entity	10	359	November 16, 2025
Understanding Array Reduction methods SystemVerilog constraint-arraysum , array-reduction-methods	10	237	June 18, 2026
Read values are wrong in UART Verification SystemVerilog	9	187	February 9, 2026
SVA to check a N-stage synchronizer output SystemVerilog SystemVerilog , assertion , System-Verilog , SVA , SVA-Assertion	9	205	December 18, 2025
Constraint Pattern problem SystemVerilog constraint-randomization	5	332	January 10, 2026
Soft constraints must be followed by an expression SystemVerilog constraint-randomization , soft-constraints , Implication-constraint	7	204	March 16, 2026
Question regarding followed by operator in SVA (#-# and #=# SystemVerilog SystemVerilog , SVA , SVA-Assertion	0	135	November 11, 2025
Detection of Interrupt in Monitor UVM UVM , virtual-interface , rose	7	278	August 28, 2026
[SVA Question] Signal 'b' has to toggle only once within 10cycle window of signal 'a' after 'a' is asserted SystemVerilog assertion , SVA , SVA-Assertion	7	290	June 28, 2026
Randomization of req signal in priority arbiter SystemVerilog constraint-randomization , Priority-arbiter	7	241	March 11, 2026
Difference of reset/configure/main/shutdown phases and run phase UVM UVM , UVM_PHASE , phase , UVM-phases , run_phase , uvm-run_phase , main_phase , run_phase-main_phase	5	280	April 20, 2026
How to set_inst_override_by_type a uvm_reg UVM	7	274	December 4, 2025
is $fell(sig_a) true when sig_a from x to 0? SystemVerilog assertion , SVA	4	252	July 13, 2026
Monitor-to-Scoreboard Connection UVM UVM	3	322	July 1, 2026
Type v/s Size cast within with clause of sum() SystemVerilog SystemVerilog , constraint-randomization , array-reduction-methods	5	206	July 15, 2026
System verilog Assertion SystemVerilog assertion	4	242	January 1, 2026
Confusion About uvm_void in UVM Hierarchy UVM UVM	3	116	May 26, 2026
SVA on intersect SystemVerilog assertion	5	228	February 24, 2026
UVM Class Hierarchy ? can any one help me by giving me the full uvm base class hierarchy structure UVM UVM	5	265	October 27, 2025
How are registers supposed to deal with resets in UVM 2020? UVM uvm_reg , reset	6	190	February 3, 2026
The difference between a looped `fork...join_none` and a serial `fork...join_none` SystemVerilog	5	151	July 7, 2026
Calling parent function via super is calling child class function SystemVerilog	4	119	February 12, 2026
Configuring agent in Active / Passive mode UVM uvm_config_db , activepassive-agent-configuration , uvm_agent , uvm_active_passive_enum	5	272	February 22, 2026
Query on generating rand 2D array with sum of set bits equal to specific value and bits must be connected to each other SystemVerilog constraint-randomization , 2Darray	4	225	January 5, 2026
Multiple dist constraints SystemVerilog SystemVerilog , constraint-dist , systemverilog-distribution-constraints	5	218	April 27, 2026
Display uvm_info including ps values UVM	7	170	November 23, 2025
Verifying synchronours fifo SystemVerilog	3	230	November 11, 2025
Assignment rules for different width & sign SystemVerilog SystemVerilog , signed , casting , assignment	5	141	July 1, 2026
UVM FACTORY Example Usage UVM uvm-factory , uvm-factory-override	2	215	December 18, 2025
Assertion failure using strong property SystemVerilog SVA , Sva-strong , strong-property , fail-action-block	7	201	February 19, 2026
What happen if the antecedent occurs or it is true, but the consequent will never occur? SystemVerilog SVA	6	134	August 16, 2026
SVA sampling of always( a ##1 b[->1] ) SystemVerilog SystemVerilog , concurrent-assertion , Embdedded-Concurrent-assertion , always-property	6	146	February 8, 2026
Calling a Task at the end of run_phase UVM UVM , UVM-phases	3	198	January 17, 2026
Size() vs $size for constraining Unpacked Arrays SystemVerilog SystemVerilog , unpacked-array , arraysize , sizearray	4	204	April 14, 2026
I need to know how many UVM active/Passive agents are required UVM UVM	4	166	April 4, 2026
UVM Driver Communication: get_next_item()/item_done() vs get()/put() — Which is Preferred in Industry? UVM UVM	5	139	June 14, 2026
Connection using modports with different signals SystemVerilog SystemVerilog , modport , interface	6	147	December 12, 2025
Expression bit-length and Associativity SystemVerilog SystemVerilog , LRM-Size-Casting	5	180	May 11, 2026
Working of $monitor SystemVerilog monitor , monitor-SV-System-Function	5	181	February 17, 2026
Question regarding the generate block SystemVerilog SystemVerilog	8	161	March 31, 2026
SystemVerilog constraint: unique addr across array of structs without auxiliary array SystemVerilog SystemVerilog , constraint-randomization , unique	3	202	January 9, 2026
VIP based verification UVM	2	223	November 27, 2025
Why create method is not part of uvm_object_wrapper? UVM uvm-factory	3	175	July 10, 2026
Weighted constraints not working SystemVerilog constraint-randomization	3	169	January 2, 2026
Confusion with the master monitor and slave monitor functionality UVM UVM , SPI-Test-Plan	3	213	December 22, 2025
Determining the bit width of operands in constraint SystemVerilog constraint-randomization , Evaluating-a-Constraint-expression , Size-Cast , Constraint-Expression	4	167	July 1, 2026
The question of disable SystemVerilog	6	136	July 13, 2026
SV Assertions using $past() SystemVerilog SystemVerilog , assertion	2	201	February 18, 2026
Where to implement memory read/write operations in UVM agent when observing packet transactions in monitor? UVM UVM	3	144	June 23, 2026
restricting sequence as long as one variable is asserted SystemVerilog SystemVerilog , assertion , System-Verilog , SVA	4	169	November 2, 2025