Verification Academy

Topic	Replies	Views	Activity
Constraint to generate a pattern SystemVerilog SystemVerilog , constraint-randomization	13	241	July 25, 2024
SVA for Invalid FSM state transition SystemVerilog assertion , System-Verilog , SVA	11	497	February 16, 2024
Assertion to check variable distance of two signals SystemVerilog SystemVerilog , assertion , System-Verilog , SVA	10	453	February 13, 2024
Writing an SVA for 3 signals SystemVerilog assertion	14	160	July 15, 2024
Unexpected results for Dynamic delay range SystemVerilog SystemVerilog , Unexpected-results-for-Dynamic-delay-range	15	939	January 16, 2024
Understanding the throughout SVA SystemVerilog assertion , SVA-Assertion	10	401	February 29, 2024
Asynchronous Stable Signal SVA SystemVerilog SystemVerilog , assertion , testbench , SVA , property	14	862	August 17, 2023
Regarding clock inheritance for sequence methods and event control SystemVerilog SystemVerilog , assertion , SVA	11	245	March 29, 2024
Making multiple constraint testbench on SystemVerilog SystemVerilog SystemVerilog , constraint-randomization	9	307	February 5, 2024
4 phase req ack SystemVerilog SystemVerilog , UVM , assertion , System-Verilog	10	109	June 7, 2024
Skipping a register field from comparison with RAL UVM RAL , uvm_ral , RAL-UVM	10	224	May 15, 2024
Assertion to check delay between two signals SystemVerilog SystemVerilog , assertion	9	697	September 19, 2023
Communication between sequence and scoreboard UVM UVM , UVM-scoreboard	13	825	August 22, 2023
How to override base sequence with virtual sequence from command line using factory? UVM UVM , uvm-factory-override	14	658	August 21, 2023
Assertion for walking 1's SystemVerilog SystemVerilog	15	1177	September 6, 2023
Discrepancy on legality of the consequent SystemVerilog SystemVerilog , SVA , system-verilog-assertion-SVA , SVA-Assertion	9	206	May 6, 2024
Logical question SystemVerilog	9	115	May 6, 2024
How to pass an array in verilog funcion SystemVerilog SystemVerilog , Verilog , FunctionArgument	10	568	December 6, 2023
Drain time is not getting set UVM UVM	9	579	September 6, 2023
$past with gating signal assertion SystemVerilog SystemVerilog	9	151	March 22, 2024
Assertion to test 3 signals where when A goes high it should for B or C to go high and checking should continue till a is high SystemVerilog SystemVerilog	11	1256	September 4, 2023
Using sequence as event contol SystemVerilog SystemVerilog , Using-sequence-as-event-contol	12	1021	October 13, 2023
How to write SVA assumption SystemVerilog SystemVerilog	18	610	August 24, 2023
Achieving Dynamic delays in SVA using subroutine SystemVerilog SystemVerilog , Achieving-Dynamic-delays-in-SVA-using-subroutine	10	1532	July 30, 2023
Legal ways to specify the leading clock in SVA SystemVerilog SystemVerilog , Legal-ways-to-specify-the-leading-clock-in-SVA	12	736	October 9, 2023
My randomization is failing UVM UVM , geting-randomization-failled	14	661	September 29, 2023
How to access a changing RTL path? UVM SystemVerilog , UVM , RTL	9	504	September 27, 2023
VERY Tough Assertion Question (Hard) SystemVerilog SystemVerilog	9	521	September 10, 2023
Difference in output using 'within' V/S 'intersect' operator SystemVerilog SystemVerilog , Difference-in-output-using-within-VS-intersect-operator	10	1069	October 2, 2023
Assigning local variable within 'or' V/S 'and' operator SystemVerilog SystemVerilog , Assigning-local-variable-within-or-VS-and-operator	11	1088	September 24, 2023
Question on muti-thread and single-thread sequences SystemVerilog SystemVerilog	11	787	August 8, 2023
Issues on Queue at receiver class UVM UVM	17	579	September 21, 2023
Assertion SystemVerilog SystemVerilog	10	800	September 4, 2023
Local variable assignment in Multithread consequent SystemVerilog SystemVerilog , Local-variable-assignment-in-Multithread-consequent	9	964	September 17, 2023
Equivalent expression for b[=0] SystemVerilog SystemVerilog , Equivalent-expression-for-b0	12	1038	October 27, 2023
Register sequences can be started on null handle UVM UVM , Cookbook-RegistersBuiltInSequences	9	484	October 23, 2023
Problems with uvm_config_db#()::get() in a class called tinyalu_agent_cfg UVM UVM	9	344	October 9, 2023
Syntax error in questasim during compilation of APB 3 UVM UVM	9	384	August 21, 2023
Using Multi-clocked intersect operator SystemVerilog SystemVerilog , Using-Multi-clocked-intersect-operator	14	702	September 5, 2023
Dynamic type casting Error UVM UVM , cast , dynamic-typecas	9	397	August 9, 2023
UVM Verification project ideas UVM	3	468	February 25, 2024
SV Proability Constraint for Number of Set Bits SystemVerilog	4	426	January 16, 2024
Assertion to check for signal propagation SystemVerilog assertion	8	477	January 15, 2024
Constraint Interview Question SystemVerilog constraint-randomization	7	801	January 23, 2024
Constraint Question : Write a constraint for 2D Array where value of an element should be different from its neighbor SystemVerilog constraint-randomization	5	542	January 15, 2024
UVM TB interview question UVM UVM	1	138	June 17, 2024
Constraint to Generate 10 bit number with set bits such that no set bits are together SystemVerilog constraint-randomization	7	411	February 17, 2024
SV Interfaces: best coding style to encapsulate functionality? SystemVerilog SystemVerilog , Interfaces	8	1255	October 12, 2023
How we can use task as function and function as task? SystemVerilog	1	112	April 3, 2024
Interview Question on UVM UVM	4	242	April 8, 2024