Repeat or for loop in assertion

SystemVerilog
1

Hi all,

I want to write an assertion with this flow:
A is going down for 100ns.
B toggle 20 times, only when A in low.
I need to check that the last edge of B happen at least 20ns before A go to high.

How can I catch the last edge?
Can I write a loop of 20 iterations?

Tried some options of loops, but nothing worked.

Thanks

2

If you don’t have a clock for signals A and B, you can use tasks.
If you have clocks, then you can use SVA
I am showing 2 untested solutions, but they look OK

// A is going down for 100ns.
// B toggle 20 times, only when A in low.
// I need to check that the last edge of B happen at least 20ns before A go to high.
bit a, b;
task automatic toggle;
  $realtime b_now;
  b_now=$realtime;
  int count;
  fork
    begin // check b
      forever begin // while (a==0)
        @(b) count++ ;
        b_now=$realtime;
      end
    end

    begin
      @(posedge a) 
      am_tdiff: assert($realtime - b_now == 20ns);
      am_numb: assert(count==20);
     end
   join_any
 endtask

   always @(negedge a) toggle(); 
//-----------
   bit a, b, clk; 
   property p; 
    realtime v; 
    int count;
    @(posedge clk) ($fell(a), v=$realtime, count=0) |->
           (@(clk) (1, v=$realtime)[*1:$] intersect a[->1]) ##0
             $realtime - b_now == 20ns ##0 count==20;
   endproperty
1 Like
3

Thanks,
I tried to do it, but understand that the require is different a bit.
A is going down - don’t know for how long.
B should toggle 22 times
I need to check that from last edge of B there are at least 8ns before A will be high.

Tried to rewrite the code you gave, but still not work to me.

could you help me please?
Thanks.

4

Show your code and testbench
Explain the requirements in more details.

5

This is the code, I’m sure something wrong, but don’t know what.

the requires:
I’m implementing SPI protocol, once CS fall, the SCLK toggle 22 times and after CS rise again.
I want to check from last edge of the clock, CS is stable at least for 8ns.

Thanks

module spi_assertios ();
 logic assert_clk = 0;
    always #1ns assert_clk = ~assert_clk;

 property wait_clock(); 
        realtime v,b; 
        int count;
        (1, v=$realtime, count=0) |->
               (@(posedge spi_qspi_vif.SCLK) (1, b=$realtime)[*1:$] intersect spi_qspi_vif.CS[->1]) ##0
                 $realtime - b == 8ns ##0 count==22;
                 @(negedge spi_qspi_vif.SCLK);
   endproperty

assert_Thss : assert property (@(posedge assert_clk) @(negedge spi_qspi_vif.CS) -> (wait_clock()) |-> )$display("Assertion assert_Thss Passed");
                 else $display("Assertion assert_Thss Failed"); 

endmodule
6

who can please help me?

7

Show us a simple module with no interfaces. Generate 2 sets of stimulus: one that passes and one that should fail.