Can anyone suggest how to write assertion for this question. once enable is high in the next clock cycle one pulse on signal a( width is 1 clk cycle) should be generated every 10 clock cycles

SystemVerilog
1 
property prop;
    @(posedge clk)
    if(enable)
      ##1 ((a) ##1 !a[*9])[*1:$];	
endproperty : prop

I tried like this. As per the question if should run infinite time but I don’t get it.

2

This works

 module m;
  bit clk, enb, a;
  bit[2:0] p0, f0, p1, f1; //  p2, f2;
  initial forever #3 clk = !clk;

 
  // if enb && a then a==0 9 more times 
  ap_a9: assert property(@ (posedge clk) enb && a  |-> ##1 !a[*9]);  

  // never a==0 occuring 10 times in a row
  ap_no10a:  assert property(@ (posedge clk) enb  |->  not(!a[*10]));  

 

  initial begin 
    @(posedge clk) enb <= 1; 
      repeat(3) begin 
        @(posedge clk) a<=1; 
         repeat(9)  @(posedge clk) a<=0; 
      end
  end
endmodule

Link to the list of papers and books that I wrote, many are now donated.
https://systemverilog.us/vf/Cohen_Links_to_papers_books.pdf

3 
module m;
  bit clk, enb, a;
  bit[2:0] p0, f0, p1, f1; //  p2, f2;
  initial forever #3 clk = !clk;

 // Need to handle border cases on "a" after the fist rise of enb.
  // if new enb then ##1 a then no a 9 more times 
 ap_a9enb: assert property(@ (posedge clk)  $rose(enb) |-> ##1 a ##1 !a[*9]); 
 
 // if stable enb && a then a==0 9 more times  
  ap_a9: assert property(@ (posedge clk) $stable( enb) && a |-> ##1 !a[*9]);
 
 // never a==0 occurring 10 times in a row
  ap_no10a: assert property(@ (posedge clk)   enb |-> not(!a[*10]));

  initial begin 
    @(posedge clk) enb <= 1; 
      repeat(3) begin 
        @(posedge clk) a<=1; 
         repeat(9)  @(posedge clk) a<=0; 
      end
  end
endmodule

Link to the list of papers and books that I wrote, many are now donated.
https://systemverilog.us/vf/Cohen_Links_to_papers_books.pdf

4

a10times_onlyPass
a10times_onlyPass1611×779 178 KB

If (enable) is stable, you also require by the assertion that ( ##1 ((a)) matches. But the previous attempt requires !a repeated 9 times.
Yoiu have a new attempt at every clock. The other attempts will cause errors

module m;
  bit clk, enb, a;
  bit[2:0] p0, f0, p1, f1; //  p2, f2;
  initial forever #3 clk = !clk;
  event e;

 // Need to handle border cases on "a" after the fist rise of enb.
  // if new enb then ##1 a then no a 9 more times 
 ap_a9enb: assert property(@ (posedge clk)  $rose(enb) |-> ##1 a ##1 !a[*9]); 
 
 // if stable enb && a then a==0 9 more times  
  ap_a9: assert property(@ (posedge clk) $stable( enb) && a |-> ##1 !a[*9]);
 
 // never a==0 occurring 10 times in a row
  ap_no10a: assert property(@ (posedge clk)   enb |-> not(!a[*10]));

  ap_prop: assert property( @(posedge clk)
    if(enb) ##1 ((a) ##1 !a[*9])[*1:$]);	 


  initial begin 
    int rp; 
    @(posedge clk) enb <= 1; 
    repeat(15)  @(posedge clk) a<=1; 
    
      repeat(10) begin 
        if (!randomize(rp) with { rp >4; rp <15; }) ;  
        //`uvm_error("MYERR", "This is a randomize error");

        @(posedge clk) a<=1; 
         repeat(rp)  @(posedge clk) a<=0; 
      end
      -> e; 
  end
endmodule