Followed by operator usage in coverage statements

SystemVerilog
1

Hello team,

I’ve been exploring the use of the “followed by” operator (#=#) and initially thought it would help with coverage by preventing false positives. However, when testing the code with coverage statements, I found that both #=# and |=> give the same coverage results! Here’s my code and the corresponding coverage statements:

My understanding:

  • b |=> c: If b is not 1 at the clock edge, it passes vacuously and still hits coverage.
  • b #=# c: If b is not 1 at the clock edge, it fails and misses coverage.

code link

2 
* `b |=> c`: If `b` is not `1` at the clock edge, it passes vacuously and still hits coverage.
[Ben] Yes, the property b |=> c  passes vacuously TRUE,
and true is true, regardless of its color. 
Thus, it hits coverage

* `b #=# c`: If `b` is not `1` at the clock edge, it fails and misses coverage
[Ben] b #=# c is saying sequence "b" if followed by property c.  If b==0, the sequence b is not a match, thus the property b #=# c` is false, and it misses coverage.
3

i can not see miss in coverage report , that’s why am asking

4

What are you getting?
You edaplaygroung is missing the +cover and the -coverage.
https://www.perplexity.ai/search/in-edaplayground-how-to-displa-Xfy1gTtvT.eWghj7SDuKgw
give me a link to an update eda run.

5
6

wow , thanks it works not with -coverage in run options
i have another question please
c_followed_by : cover property (seq_a #=# b)
$info (“\033[32m [%0t] c_followed_by pass”,$time); else
$info (“\033[32m [%0t] c_followed_by fail”,$time);

why can not i use else statement in cover statement as assertions?

7

i think it was assertion not coverage , please check the link
EDA Playground , it give miss count for assertions only not coverage
coverage still got the same problem

8

I got coverage EDA Playground

/test_followed_by/c_followed_by test_followed_by Verilog SVA testbench.sv(15) 1 Covered

/test_followed_by/c_imp test_followed_by Verilog SVA testbench.sv(18) 1 Covered

a vasuously pass property is a pass.
the cover statement cannot fail
Not clear on your issue

9

the coverage won’t display the miss of followed by , that was my question
you have two variables fw and mp , both are 1 in the end of the simulation :)

10

functional coverage is a measure of what functionalities or features of a design have been exercised in simulation.
Those properties were true, and thus were covered.
What “miss” are you talking about?
By “miss” you mean failures?

11

yes , followed by , should cause failure?

12

cover directives can only pass, they never fail. If you need to know about failure, use assert. That gives you coverage that is passed, as well as notifying you when it fails.