Generate the sequence using constraint

SystemVerilog
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1

Generate a constraint for the sequence 101100111000… without using pre and post randomize

2

This exact question was asked two days ago.

3

Below generic logic works

module example;
  // 16-bit wide vector, adjust size as needed
  logic [15:0] bitstring;

  // Constraint to ensure the condition that for each number of `1`s,
  // the number of `0`s following them is equal or greater.
  constraint ones_zeros_constraint {
    // Count number of ones and zeros
    int ones, zeros;

    // Find number of ones and zeros
    ones == $countones(bitstring);
    zeros == bitstring.size() - ones;

    // Ensure that the number of zeros is at least as many as ones
    zeros >= ones;
  }

  // Test stimulus to generate random valid bitstrings
  initial begin
    // Apply the constraint and print the generated bitstring
    foreach (bitstring[i]) 
      bitstring[i] = $random; 

    // Display the random bitstring
    $display("Generated bitstring: %b", bitstring);
    assert(ones_zeros_constraint) else $fatal("Constraint failed!");
  end
endmodule
```verilog