Hi i have written a boiler plate code for simple UVM environment. All the phases are executing, starting with build , connect and control is going to task run_phase of test but seq.start(seqr) ; is not executing , seq is not starting at all, i tried all the possible solution but not able to run it. Help me to come out of this??
Without showing code, it’s difficult to provide assistance. How do you know the sequence isn’t starting? Are you using objections properly? Perhaps there is an issue in another part of the testbench.
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okay… sure i am sharing the code here.
`include "package.sv"
class base_test extends uvm_test;
`uvm_component_utils(base_test)
usart_env env_o;
base_seq seq;
function new(string name = "base_test", uvm_component parent );
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
env_o = usart_env::type_id::create("env_o", this);
seq = base_seq::type_id::create("seq"); // argument should be sequence name
`uvm_info(get_type_name(),$sformatf("Env and seq is created "),UVM_MEDIUM);
if(seq!= null) begin
`uvm_info(get_type_name(),$sformatf("Run phaseof test , :: Seq is created , checking if seq is null"),UVM_MEDIUM);
end
endfunction: build_phase
function void end_of_elaboration_phase(uvm_phase phase);
super.end_of_elaboration_phase(phase);
uvm_top.print_topology();
endfunction
virtual task run_phase(uvm_phase phase);
super.run_phase(phase);
phase.raise_objection(this);
`uvm_info(get_type_name(),$sformatf("objection is raised "),UVM_MEDIUM);
seq.start(null);
`uvm_info(get_type_name(),$sformatf("seq is staring using .start method "),UVM_MEDIUM);
phase.drop_objection(this);
endtask
endclass: base_test
and my sequence is
class base_seq extends uvm_sequence#(usart_seq_item);
`uvm_object_utils(base_seq)
usart_seq_item req;
function new (string name = "base_seq");
super.new(name);
endfunction
virtual task body();
`uvm_info(get_type_name(), "Base seq: Inside Body", UVM_LOW);
`uvm_do(req);
endtask
endclass
here is the log file
UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3
UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(216) @ 0: reporter [Questa UVM] questa_uvm::init(+struct)
Interface is instantiated sucessfull
Top :: Triggering the test
UVM_INFO @ 0: reporter [RNTST] Running test base_test…
UVM_INFO usart_test.sv(18) @ 0: uvm_test_top [base_test] Env and seq is created
UVM_INFO usart_test.sv(20) @ 0: uvm_test_top [base_test] Run phaseof test , :: Seq is created , checking if seq is null
UVM_INFO usart_env.sv(29) @ 0: uvm_test_top.env_o [usart_env] Env :: Agent is created and interface is set created
UVM_INFO usart_drv.sv(15) @ 0: uvm_test_top.env_o.agt.drv [usart_drv] In build phase DRIVER
UVM_INFO usart_agt.sv(28) @ 0: uvm_test_top.env_o.agt [usart_agt] CONNECT PHASE
UVM_INFO usart_agt.sv(30) @ 0: uvm_test_top.env_o.agt [usart_agt] DRIVER AND SEQR ARE CONNECTED
UVM_INFO usart_env.sv(41) @ 0: uvm_test_top.env_o [usart_env] connect phase exiting
UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:
--------------------------------------------------------------
Name Type Size Value
--------------------------------------------------------------
uvm_test_top base_test - @471
env_o usart_env - @478
agt usart_agt - @489
drv usart_drv - @607
rsp_port uvm_analysis_port - @622
seq_item_port uvm_seq_item_pull_port - @614
mon usart_mon - @630
item_collect_port uvm_analysis_port - @637
seqr usart_seqr - @498
rsp_export uvm_analysis_export - @505
seq_item_export uvm_seq_item_pull_imp - @599
arbitration_queue array 0 -
lock_queue array 0 -
num_last_reqs integral 32 'd1
num_last_rsps integral 32 'd1
--------------------------------------------------------------
UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_test_top raised 1 objection(s): count=1 total=1
UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_top added 1 objection(s) to its total (raised from source object uvm_test_top): count=0 total=1
UVM_INFO usart_test.sv(37) @ 0: uvm_test_top [base_test] objection is raised .
Objection is getting raised but next statement is not executing
Since your sequence is generating sequence_items (usart_seq_item), you must start it on an appropriately typed sequencer. This is typically the sequencer of your agent.
I would expect to see something like in your test:
task run_phase(uvm_phase phase);
seq = base_seq::type_id::create("seq"); // argument should be sequence name
phase.raise_objection(this);
`uvm_info(get_type_name(),$sformatf("objection is raised "),UVM_MEDIUM);
seq.start(env_o.usart_agent.m_seqr);
`uvm_info(get_type_name(),$sformatf("seq is staring using .start method "),UVM_MEDIUM);
phase.drop_objection(this);
endtask
HI, yes!! i have tried it multiple times but its the same results.
i am starting like
seq.start(env_o.agt.seqr);
Result is same.
So does the entire test stop and not finish? Do you get a UVM timeout message?
Perhaps your driver is not functional and not requesting/driving items from the sequencer?
If you could post the entire environment on EDA Playground so that we can see everything, it would be helpful.
okay… i am posting the eda link, my plan to verify the uart register set but i was not able to start the sequence so i am stuck there .
Please check if any mistakes is there
Your issue is that you have no clocks in your design, resulting in everything occurring in 0 time.
Also, you have a forever loop in your monitor. Without any clocks or other blocking methods, your monitor prevents your environment from advancing.
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so please provide the solution for this, should i add the clock and drive as per the clock.
help me to find the solution for this.
yes… right… i removed the forever loop and its executing now.