Need help to generate pattern 10110111011110111110

SystemVerilog
1

Can u help generate pattern 10110111011110111110 using SV constraint.

2 
class A;
  rand bit [19:0] pattern;
  constraint c { pattern == 20'b10110111011110111110;}
endclass

Next question?

3

Amazing. Thanks.
Next question is if there is any generic way to write this for extending this pattern.?

4 
class pattern;
  rand bit [19:0] data;
  
  constraint c{
    foreach(data[i]) {
      if(i inside {1,4,8,13,19}) 
        data[19-i] == 1'b0;
      else
        data[19-i] == 1'b1;
    }
  }
endclass