Assertion for signal toggling

SystemVerilog
1

I wanted to write an assertion to check the toggling of signal I used the below code property toggle; @(posedge clk) ## [0:$] $changed (a); endproperty assert property (toggle) $info (“A is toggling : Assertion pass”); else $error (“A is not toggling : Assertion fail”);

But here the problem is when the is signal a is not toggling (“0” throughout the simulation) and it is completely zero the assertion is not getting triggered and the assertion is not throwing any message

2

Because it is not toggeling,the assertion does not become active.

Please try
property toggle;
@(posedge clk)
(!$stable(a) |-> $stable(a)) ;
endproperty

3

Your requirements are not very clear. You want to check that signal sig eventually toggles. Also, you may want to
the check to occur after things settle (a rise of reset_n, or ready signal).

initial begin 
  wait(ready);  // precondition to the start 
  ap_sig_toggle: assert property(@(posedge clk) 
     s_eventually $changed(sig)); 
  // another option 
  ap_sig_toggle2: assert property(@(posedge clk) 
     strong($changed(sig)[->1]));
end

Ben Cohen Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.
https://systemverilog.us/vf/Cohen_Links_to_papers_books.pdf

4

Thanks for the reply,

Let me put this in correct way, I have a signal “a” which is an output signal and I wanted to check the signal “a” getting toggle any point during the simulation. Since it is an output signal we have no idea when the signal will toggle, It can be at the starting or at the end.

I tried using strong and s_eventually but the problem here once the signal toggles the assertion passes and if the signal is coming at the starting of simulation It toggles for some clock cycle and then goes completely zero and the assertion keeps checking for the condition and it starts failing. Even after the condition is satisfied at the starting.

So I wanted to know is there any way I can disable the assertion once my condition is satisfied.

5
  1. Did you miss the fact that my assertion had ONE attempt because it was within an initial statement following a possible time zone (like a system reset).
    With one attempt, when the signal toggles that assertion is satisfied. You have no other attempts to test for a signal toggle.
  2. If you insist on having multiple attempts, you could use the action block to reset an enable signal. For example:
bit done; 
p_sig_toggle3: assert property(@(posedge clk) 
     !done |-> strong($changed(sig)[->1])) done=1;
// Upon a pass, set done to 1, thus disabling any more attempts to this assertion.
1 Like
6

Should be just
property toggle
@(posedge clk)
signal |-> [1:$] !signal;
endproperty.