Dave Rich is a principal instructor at Siemens EDA and is responsible for defining and deploying advanced verification methodologies. Most recently, Dave Rich was a Verification Architect in the Product and Solutions Ecosystems team at Siemens EDA, responsible for the Verification Academy’s content and forum discussions. He has over three decades of design and verification experience in simulation and synthesis technologies. He is actively involved in SystemVerilog standardization, serving as Technical Chair of the IEEE 1800 Working Group and on the Design and Verification Conference steering committee.
Dave started his career as a design and verification engineer at Data General, evaluating one of the earliest versions of Verilog from Gateway Design Automation. He later joined them as one of their first application engineers. At Gateway, he helped develop and promote Verilog to become the leading language for ASIC design worldwide. After Cadence acquired Gateway, Dave worked on donating the LRM to the Open Verilog International organization, which eventually became the IEEE 1364-1995 standard. Later, he worked on simulation and synthesis technologies acquired by Cadence and Synopsys. At Siemens, Dave was an original designer of the Advanced Verification Methodology (AVM) and later the Open Verification Methodology (OVM), which became the Universal Verification Methodology (UVM). This is now the IEEE 1800.2 UVM standard.
Dave has a Bachelor of Science in Electronic Computer Engineering from the University of Rhode Island. When not online, Dave spends most of his time outdoors biking, hiking, boating, XC-skiing, and gardening.
