Dominik Mentel
Dominik Mentel is a young and enthusiastic ASIC Verification Engineer with three years of hands‑on experience contributing to the development and verification of complex ASICs within Siemens Factory Automation, specializing in PROFINET technology. He focuses on creating robust, scalable verification environments at the module level, ensuring functional correctness across highly integrated industrial automation products.
With a strong background in SystemVerilog‑based verification, constrained‑random testing, and coverage‑driven methodologies, Dominik supports the full verification lifecycle - from environment development to debugging and closure. Committed to supporting and adopting emerging verification technologies, he has already collaborated with Siemens EDA on advanced methodologies and innovative tooling to further enhance verification quality and efficiency.
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