Progyna Khondkar
Progyna Khondkar, is a low power design & verification expert and senior verification engineer at Siemens EDA in the Design Verification Technology Division (DVT). He holds two patents and authored; [i]Low Power Design and Power Aware Verification[/i], that will be published from Springer in September 2017. He also has numerous publications in power aware verification. He has strong focus on electronics, computer and information science education, research and teaching experiences in top level universities in Asia. He has been working for hardware/software design, development, integration, test and verification in the world class ASIC & Electronic Design Automation (EDA) companies for last 15 years. He holds a Ph.D Computer Science and a senior member of IEEE. He also serves as a member of editorial board and reviewer of Journal of Information, IEEE Transactions on Computer-Aided Design of Integrated Circuit and Systems, IEEE Transactions on Computers and Journal of VLSI Design and Verification (JVLSIDV).
Content by Progyna Khondkar
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Low Power Coverage: The Missing Piece in Dynamic Simulation
Simulation Jan 07, 2020 Progyna Khondkar Article -
Effective Elements List and Transitive Natures of UPF Commands
Standards Jan 07, 2020 Progyna Khondkar Article -
UPF Information Model: The Future of Low-Power Verification Today
Low Power Aug 28, 2018 Progyna Khondkar Paper -
Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF
Low Power Mar 20, 2017 Progyna Khondkar Paper
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