If You Don’t Know, Now You Know: Terminal Boundary Dictates Power Aware Macros

Integration of soft and hard macros with low power designs and conduct power aware (PA) verification are always complex and cumbersome. Specifically, in bottom-up integration perspective, the extents of power domain boundary, terminal boundary, ancestor-descendant relations, power intent confinement, driver-receiver supply contexts, power states expectations, simulation state behavior, corruption semantics etc. for these macros were not well defined until UPF 3.1 (IEEE 1801-2019). As a consequence, low power macro verification solutions were not always intuitive, portable or standard.

This paper distinctively studies the inherent integration features of soft and hard macros that are inevitable for low power designs today. This has been done by thoroughly identifying the semantic gaps between physical interpretations of macros with their low power orientations. With real design examples, we provided simple and manageable macro verification solutions that are portable, comply with UPF 3.1 standards and re-usable in consecutive projects.

This will also address verification challenges between flat frontend simulation flows to the hierarchical backend flows. Our motivation is to create a complete low power integration and verification solution for soft and hard macros that will benefit the design, verification, integration, implementation, as well IP vendor industries.

Introduction

IP (or macros) like memories, IOs, PHYs etc. in general, play crucial roles in developing every chip design today. There are soft (synthesizable RTL) and hard (already synthesized, sometimes placed and routed) macros that are generally available for integration in system level designs, like SoCs. In the UPF based low power design, verification and implementation flow (DVIF), macros introduce additional layers of complexities. Specifically, this is because of inadequate knowledge about the identification of macros in UPF boundary concepts and then mapping of additional power artifacts – like driver or receiver supplies, power strategies, terminal boundaries – around them.

On one side, this was due to the lack of UPF standards that will help to identify and map all the power artifacts (ranging from power domain to different power strategies) around the macros. On the other hand, macro integration to the entire design and subsequently conduct power aware (PA) verification lacks in a coordination of knowledge from the physical implementation perspective.

In general, soft macro are part of a larger RTL subtree before implementation. But the fundamental problem arises when they are hardened (synthesized). A standalone self-contained UPF is mandatory for implementation to accurately model the outside environment view of the macro based on the internal power supplies. Because implementation is hierarchical, but verification is required in full SoC level as flat view. This may expose conflicting different views for implementation and verification.