Adding virtual qualifier to predefined SV Functions

SystemVerilog
, ,
1

Hi Forum,

In the following code

class root;

 function void abc();

  // Some logic

endfunction

endclass

class ext extends root;

  function void virtual abc();

  // Some logic 

  endfunction

endclass

A user-defined function in base class could be non-virtual whereas in the extended classes it would be virtual ( and remains virtual even if one were to extend class ext )

However on trying to add virtual keyword to pre_randomize() and post_randomize() I observe a compilation error

As per LRM these functions are not virtual but behave as one due to implicit call before and after randomization()

Does the LRM say they can’t be declared as virtual ?

Thanks