Dave Rich is a Verification Architect in Product & Solutions Management Ecosystem team at Siemens. He is chartered with cultivating the content of the Verification Academy and moderating its forum discussions. He is also responsible for widespread adoption of various standards and testbench methodologies. Dave brings over three decades of design and verification experience to bear on developing advanced verification methodologies. He has been actively involved in the standardization of SystemVerilog, via Accellera and now the IEEE, where he is serving as Technical Chair of the SystemVerilog IEEE 1800 Working Group. Dave was one of the original designers of the Advanced Verification Methodology (AVM), and later the Open Verification Methodology (OVM). That became the basis of the Universal Verification Methodology(UVM) Prior to that, Dave worked on early simulation and synthesis technologies at Cadence and Synopsys getting people to adopt Verilog.
