Functional Verification of Digital Logic
Dive into the world of functional verification with our advanced master’s-level course, developed in collaboration with North Carolina State University. This comprehensive program covers all essential aspects of creating sophisticated constrained-random, coverage-driven testbenches using SystemVerilog and UVM.
-
Track Overview
This track is structured into ten sessions, each comprising multiple concise video lessons averaging seven minutes in length. Gain hands-on experience and deepen your understanding of functional verification through practical examples and expert guidance.
-
Meet the Instructors
-
Sessions
-
Verification Process Overview
This session, with five lessons shown in the tabs below, covers the Verification Process: where to start, what needs to be done, and when verification is complete. Learn about directed testing, constrained-random stimulus, and coverage metrics. Explore testbench tasks, component roles, and reuse strategies. Understand UVM test flow, from selection to completion. By the end, you’ll master effective verification strategies. -
Creating and Using a Test Plan
This session, with two lessons shown in the tabs below, covers the purpose and content sources of a test plan. Learn how to finalize a test plan and use its fields to measure coverage achievement and identify gaps. By the end, you’ll understand how to effectively create and utilize a test plan for comprehensive verification. -
Data Types and Procedural Statements
This session, with four lessons shown in the tabs below, covers SystemVerilog’s default data types, variable declaration, and type casting. Learn about the two basic array types, their usage, and indexing. Explore the array types available and the methods for their use. Understand selection, loop, and jump statements in SystemVerilog. By the end, you’ll have a solid grasp of these fundamental concepts. -
Creating and Using Functional Coverage
This session, with four lessons shown in the tabs below, covers verification metrics and coverage classifications to determine what’s verified, what’s not, and when we’re done. Learn about SystemVerilog constructs for creating a functional coverage model and recording coverage data. Explore creating reusable covergroups, covergroup methods, extracting coverage results, and controlling SystemVerilog cover capabilities. Understand how to sample covergroups and where to add them in your testbench. -
Creating and Using Constrained Random
This session, with five lessons shown in the tabs below, covers the fundamentals of constrained random verification and basic SystemVerilog constructs for effective testing. Identify and correct Verilog constraints influenced by operator bit width, signed results, and precedence. Understand how bit-width and signed results errors contribute to randomization errors. Apply SystemVerilog constructs for desired random distributions and explore random variables and constraints in your testbench. -
Connecting the Testbench to the Design
This session, with three lessons shown in the tabs below, covers the connection between the Testbench and the DUT (Device Under Test). Learn about interfaces, signal descriptions, and modeling signaling delays. Understand protocol signaling, its driving and monitoring, and the emulatability of the implementation in hardware. By the end, you’ll master connecting your testbench to the design effectively. -
Execution Semantics and Synchronization
This session, with three lessons shown in the tabs below, covers SystemVerilog constructs for controlling simulation timing and synchronizing testbench components. Learn about SystemVerilog threads for modeling concurrent processes and creating complex testbenches. Understand the use of semaphores and mailboxes for managing concurrent processes effectively. By the end, you’ll master execution semantics and synchronization in your simulations. -
Object-Oriented Programming in SystemVerilog
This session, with eight lessons shown in the tabs below, covers the history of Object-Oriented Programming and SystemVerilog-specific OOP terminology. Learn the basics of SystemVerilog classes, class properties, methods, and static properties. Understand how to derive and extend classes, utilize polymorphism, and explore multiple OOP design patterns. By the end, you’ll master OOP concepts and their applications in SystemVerilog. -
Testbench Customization in UVM
This session with three lessons shown in the tabs below, covers UVM Factory core functionalities, including registering UVM objects and components. Learn why the standard constructor may not always be optimal and how UVM leverages the Factory Pattern for customization. Understand altering UVM component types without code changes exchanging information between UVM objects/components with the configuration database. By the end, you’ll master flexible and adaptable testbench customization in UVM. -
UVM Stimulus, Tests, and Regressions
This session, with four lessons shown in the tabs below, covers defining tests in UVM, sharing default setups, and ensuring tests end correctly. Learn about transactions, defining transaction objects, and composing them. Understand sequences, their communication with drivers, and initiating them. Explore UVM virtual sequences, coordinating other sequences, and tailoring them to your environment. By the end, you’ll master creating complex scenarios to uncover bugs.
-