UVM Stimulus, Tests, and Regressions
This session, with four lessons shown in the tabs below, covers defining tests in UVM, sharing default setups, and ensuring tests end correctly. Learn about transactions, defining transaction objects, and composing them. Understand sequences, their communication with drivers, and initiating them. Explore UVM virtual sequences, coordinating other sequences, and tailoring them to your environment. By the end, you’ll master creating complex scenarios to uncover bugs.
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UVM Stimulus, Tests, and Regressions
How Do I Write a UVM Test?
You will learn what a test in UVM is, how to share default setup information across multiple tests, and how to ensure your test ends at the right time. By the end of the lesson, you will understand how to define tests in UVM to customize your testbench environment and invoke specific sequences to achieve your test plan goals.
How Do I Model Communication?
You will learn what a transaction in UVM is, how to define a transaction object, and how to compose transaction objects from other transactions. By the end of the lesson, you will understand how to define transactions in UVM to represent the communication between elements of your test environment.
How Do I Stimulate My Design?
You will learn what a sequence in UVM is, how a sequence communicates with a driver, and how to start a sequence as part of your test. By the end of the lesson, you will understand how to define sequences that send transactions to the driver to create specific behaviors in your DUT, and how to initiate sequences from your test.
How Do I Create Complex Test Scenarios?
You will learn how a UVM virtual sequence coordinates the execution of other sequences and how to tailor your virtual sequence to your UVM environment. By the end of the lesson, you will understand how UVM virtual sequences allow you to define combinations of other sequences to create complex scenarios that generate traffic on multiple interfaces of your design, making it more likely to uncover unanticipated bugs.
