Verification Process Overview
This session, with five lessons shown in the tabs below, covers the Verification Process: where to start, what needs to be done, and when verification is complete. Learn about directed testing, constrained-random stimulus, and coverage metrics. Explore testbench tasks, component roles, and reuse strategies. Understand UVM test flow, from selection to completion. By the end, you’ll master effective verification strategies.
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Verification Process Overview
Introduction to Functional Verification
You will learn about the Verification Process, addressing three key questions. First, where to start? Even verifying a small design can be daunting. Starting right is crucial as it saves time and minimizes bug escapes. Second, what needs to be done? Each design has unique features to verify. Understanding required tasks is vital for planning, managing, and completing verification. Lastly, when is verification done? This common question arises as we near a project’s end.
Understanding the Two Main Testing Approaches
You will learn about directed testing and constrained-random stimulus, the two main testing strategies. We’ll discuss where to apply each strategy and how to measure testing completeness using coverage metrics. By the end of this lesson, you’ll have a solid understanding of how to effectively apply these strategies in your verification process.
What is a Reusable Testbench?
You will learn about testbench tasks, component roles, and customization for varied applications. You will also learn how to reuse components across projects, enabling efficient 'horizontal reuse'.
How Can I Reuse Testbench Components?
You will learn how to build and customize reusable testbench components. Discover 'vertical reuse' from block level to system level in your project.
UVM Test Flow
You will learn the flow of a UVM test: selecting, starting, understanding stages, ending, and the roles of testbench components.
