Browse all content in Siemens Verification Academy with the tag Low Power

June 2019

• Reusable UPF - Transitioning from RTL to Gate Level Verification

  Low Power Jun 11, 2019 pdf

May 2019

• Random Directed Low-Power Coverage Methodology - A Smart Approach to Power Aware Verification Closure

  Low Power May 22, 2019 Madhur Bhargava pdf

March 2019

• Effective Elements List and Transitive Natures of UPF Commands

  Low Power Feb 28, 2019 pdf

February 2019

• Low Power Apps: Shaping the Future of Low Power Verification

  Low Power Feb 28, 2019 pdf

• Effective Elements Lists and the Transitive Nature of UPF Commands

  Low Power Feb 25, 2019 Progyna Khondkar Article

• Low Power Verification Forum

  Low Power Feb 05, 2019 Gordon Allan Webinar

January 2019

• Industry Advancements Required to Close the Power Management Verification Gap

  Low Power Jan 28, 2019 Sriram Hariharan Webinar

• Deploying A Metrics Driven Low Power Methodology for Your RTL IP

  Low Power Jan 28, 2019 Qazi Ahmed Webinar

• Low Power Verification & Analysis with Emulation

  Low Power Jan 28, 2019 Shantanu Samant Webinar

• Productive Low Power Debug Across All Engines and Flows

  Debug Jan 28, 2019 Gordon Allan Webinar

November 2018

• A New Approach to Low Power Verification: Power Aware Apps

  Low Power Nov 28, 2018 Madhur Bhargava, Awashesh Kumar - Siemens Eda Article

August 2018

• UPF Information Model: The Future of Low-Power Verification Today

  Low Power Aug 28, 2018 Progyna Khondkar Paper

• UPF Information Model - The Future of Low-Power Verification Today

  Low Power Aug 28, 2018 Progyna Khondkar pdf

• Power Aware Simplifies Parametric PA-SIM Regression

  Low Power Aug 02, 2018 pdf

June 2018

• Part 2: Power Aware Static Verification – From Power Intent to Microarchitectural Checks of Low-Power Designs

  Low Power Jun 29, 2018 Progyna Khondkar Article

March 2018

• Comprehensive Metrics-Based Methodology to Achieve Low Power SoCs

  Low Power Mar 07, 2018 Ellie Burns Webinar

• SATA Specification 3.3 Gaps Filled by SATA QVIP

  Verification IP Mar 01, 2018 Naman Saxena, Nitish Goel, Rajat Rastogi - Siemens Eda Article

• From Power Intent to Microarchitectural Checks of Low-Power Designs - Part 1

  Low Power Mar 01, 2018 Progyna Khondkar Article

December 2017

• PA GLS: The Power Aware Gate-level Simulation

  Simulation Dec 06, 2017 Progyna Khondkar Article

August 2017

• Low-Power Design using High-Level Synthesis for Automotive Image Sensor

  High-Level Synthesis Aug 07, 2017 pdf

March 2017

• Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF

  Low Power Mar 20, 2017 Progyna Khondkar Paper

• Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF

  Low Power Mar 20, 2017 Progyna Khondkar pdf

February 2017

• Artifacts of Custom Checkers in Questa Power Aware Dynamic Simulation

  Low Power Feb 28, 2017 Progyna Khondkar Article

January 2017

• The Fundamental Power States for UPF Modeling and Power Aware Verification

  Standards Jan 04, 2017 Verification Methodology Team Article

• Is Your Power Aware Design Really X-Aware?

  Simulation Jan 03, 2017 Verification Methodology Team Article