VA Live - Hudson, MA

Tuesday, June 9, 2026 | 9:00 AM - 5:00 PM EDT

This seminar empowers design engineers and verification teams with knowledge and tools for advanced AI automation and intelligent verification.

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BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

New Episode!

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

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DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

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New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

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SIEMENS Verification Academy

Shift Left at Scale: Siemens Factory Automation’s Journey to Consistent RTL with Questa Lint

In this User2User Europe session, you will learn that Siemens Factory Automation successfully adopted Siemens EDA Questa Lint to strengthen RTL quality and support a modern CI/CD driven development flow. This session highlights how Questa Lint was integrated into Siemens Factory Automation’s design workflow, unexpected RTL issues uncovered, highly configurable checks and centralized rulesets enabled consistent coding practices.

Dominik Mentel Lars Wolf

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Full-access members gain access to our free tools and training, including our full library of articles, recorded sessions, seminars, papers, learning tracks, in-depth verification cookbooks, and more.

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