“Just like a Verification Plan, having goals and making sure that you have the right resources in place will help you get your job done.”
Welcome to our exciting DAC 2022 issue of Verification Horizons.
My family was finally able to mark an important milestone a few weeks ago when we attended my son’s delayed-due-to-Covid graduation ceremony at Georgetown University. David actually graduated in 2020 magna cum laude with a Bachelor of Science degree in Physics and a minor in Mandarin, and we really appreciated the university giving us the opportunity to recognize this accomplishment formally by hosting the in-person ceremony when they were able. We were impressed at how many of the 2020 graduates came back to celebrate with their former classmates.
You can imagine how proud I am of David, but I wanted to relate a small piece of the weekend experience that we had apart from the graduation ceremony itself. It actually shows the importance of planning which, as I have mentioned before, is one of my wife’s specialties. She has been watching the “PandaCam” webcam to follow the giant pandas at the National Zoo. So, when we found out that we were going to be in Washington, DC for David’s graduation, we naturally wanted to see the pandas (especially Xiao Qi Ji, the baby) in person. I’ll spare you the details, but by planning everything out, we managed to have just enough time to zip into the Zoo, head straight to the panda exhibit to spend a little time with them and still make it to the airport in time for our flight home. Just like a Verification Plan, having goals and making sure that you have the right resources in place will help you get your job done.
Our first article in this issue is “Back to the Future with Formal Property Checking” by my long-time colleague and friend, and everyone’s favorite formal verification guru, Harry Foster. In his always informative and entertaining style, Harry gives us an update of an article he wrote way back in 2010 on how to apply formal verification to any design.
As Harry discovered, and you will too, as much as the technology has changed in the last twelve years, the overall process and benefits of applying formal haven’t changed that much.
We follow that up with Part 2 of “Getting to Know Visualizer” by another long-time colleague and friend of mine, Rich Edelman. Following up on Part 1 from our March, 2022 issue, Rich will walk us through more of the powerful and useful features of our Vizualizer Debug Environment, like Driver Tracing, X Tracing, Memory and Class debugging, and some unique live-debug capabilities as well.
Next, we have “The Democratization of Digital Methodologies for AMS Verification” where my colleague Sumit Vishwakarma talks about a paradigm shift happening to adopt digital verification techniques for functional verification of analog and mixed-signal designs. In this article, Sumit discusses these digital-centric mixed-signal verification methodologies and explores how they can help to improve SoC verification throughput and time to market.
In “Unblocking the Full Potential of SSDs Using Zoned and Key Value Namespaces,” we get a great introduction to the concept of namespaces for nonvolatile memory (NVM) systems to implement solid state drives (SSDs). Then comes a great discussion of how our NVMe Questa Verification IP (QVIP) component lets you verify many different aspects of this protocol.
In “Bringing 5G NR Radio Frame Generation and Analysis to the Veloce X-STEP Product Family,” introduces us to the key pieces of a 5G New Radio system, and how the Veloce X-STEP IQ Toolset allows us to do some of the key verification of the radio frequence (RF) and physical layer (PHY) testing in the digital domain.
Next, we have “Speeding OTN Verification Using Emulation,” in which we learn about Optical Transfer Networks (OTN), and the complexities of verifying OTN protocols. We will see how the combination of Siemens’ Veloce Transactor Library for OTN and our GUI-based Virtual OTN solution gives you the power to control stimulus, monitor responses and visualize the protocol to simplify debugging of this beast of a verification challenge.
We begin our Partners’ Corner section in this issue with Part 2 of “Reflections on Users’ Experiences with SVA” by our recurring guest, SVA expert Ben Cohen. Following up on Part 1 from our March, 2022 issue, Ben completes his reflections with some important points about four relationship operators in SVA.
Next, my friend Eileen Hickey, from Doulos, provides us with her top-ten list of “Easy Testbench Speedups” in SystemVerilog and UVM. This list includes some great insights on how to approach your verification task with an eye towards the practical performance impact they can have on how quickly you can get your job done, which is really the ultimate goal, isn’t it?
We conclude this issue with two great articles on Functional Safety. Our friends at Veriest start us out with “Functional Safety Verification Challenges for Automotive ICs,” in which they share some of the lessons they’ve learned in trying to verify automotive IC designs within the confines of the ISO 26262 standard, particularly distinguishing between “classical” functional verification tasks and functional safety verification tasks.
And last, but certainly not least, our friends from Silicon Interfaces walk us along “The Path to a Safety Mechanism on an Unsafe PCIe® Sub-Module Using Siemens EDA Austemper,” where they illustrate the implementation of Safety mechanisms on an unsafe design using Austemper to generate alarms for Fault List detection and to ensure Safety using a duplication method.
Editor, Verification Horizons
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