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As a Doulos ‘techie’, I train over 100 engineers in SystemVerilog and UVM each year. I do believe quite soundly, that the effort of simulation verification is an art, supported by the language. So, regardless of the language, I have a ready list of useful testbench coding strategies to achieve faster regression CPU cycle execution. This means more regression tests executed in the same amount of ‘wall-clock’ time!
Often, an engineer wants to write testbench code by looking at online examples. However, these examples are usually written more to indicate what you could do, rather than what you should do, in the interests of CPU cycle usage. Now, if you start at the unit test level, which is excellent because you get to wiggle ALL the inputs
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